Delay of ASRCs in ADAU1772
Hello,
I am looking into taking a stream of audio from a mic, through the ADC, out to Serial Port, back in through the Serial port, through the DSP core and then out to the DAC. I understand that 38 uS (or 76 uS when running at 96kHz sampling rate) end-to-end delay can be achieved with just a "pass through" on the DSP (and I was able to measure and achieve that with my setup on the EVAL board), but I want to include sending out the I2S port and getting audio data back. So far, an audio pass through program on an ARM M4 processor over I2S gives me 200 uS delay when running the ADAU1772 ADC at 96k, and the Serial port also at 96k. I understand there could be latency involved in my processing, but I wanted to know if the ASRC is contributing to this delay. Also, should there actually be any sample rate converting at all if the sample rates across the board are the same?
Thanks
adau1772
Integrated/Special Purpose A/D Converters
Audio CODECs
Hi salggarcia,
I performed a latency measurement from the ADC to the serial port with ADC decimating to 96 kHz and the ASRC/serial port also set to 96 kHz. I measure this latency to be about ~99 us. I inject a low frequency square wave into the ADC and compare the square wave edge to the first time the MSB toggles in the I2S stream. The results are pretty consistent. This would mean in this system our ADC + Serial Port are about half of your total latency. Could you let me know how you are measuring your latency?
Sorry for the delay. I'm actively working with one of our digital designers to understand the mechanism of the ASRC when the ratio is 1/1. I'll let you know when I get some more detail.
Regards,
-BillJ
Hello Bill,
I am doing the same setup, looking at the edge of a square wave, but the chain is:
into the ADC -> Serial out -> CPU I2S interfacing (just passing input to output) -> Serial in -> straight through DSP Core -> out to DAC and looking at the transition of that square wave on the output (200 us).
If their is similar delay on the input ASRC then it would make sense for it to add up to ~200 us. I'm just wondering if there is any way to get around this if the ratio is 1:1. As we are trying to characterize our system, its important for us to know all the delays associated with each part in the chain.
Thanks
-Sal
Hi Sal,
The delay on the input ASRC is the same, so you are correct in your understanding and this does corroborate your measured delay. Unfortunately, there is no way to either route around the ASRCs, or decrease the delay through that block so I think 200 us is your baseline. It does also seem like the delay in the CPU(passthrough) is close to negligible.
Regards,
-Bill
Hello Bill,
That's important to note thanks. Right now I am trying to find a scheme to be able to get the exact delay that the ASRCs themselves introduce, which is useful for our measurement purposes to use this part. Would you be able to provide this information or an idea of how to measure it, and if it varies with what sampling rate you choose to convert from? Hard numbers are real important for our application.
Thanks,
-Sal
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