ADAU1701 working at 176.4K/192K with trouble

Hi all,

my project is using one ADAU1701 to do audio processing. SoC play/decode audio file, output the CLK/Data, feed them into ADAU1701, and after the audio processing, ADAU1701 output CLK/Data to a DAC/AMP to driver a speaker.

I use an oscilloscope to monitor the signal, the SoC output as table below:

Audio File SR
FS Ratio
MCLK
BCLK
LRCLK
DATA

44.1K
256
11.2896M
2.8224M
44.1K

48K
256
12.288M
3.072M
48K

88.2K
256
22.5792M
5.6448M
88.2K

96K
256
24.576M
6.144M
96K

176.4K
128
22.5792M
11.2896M
176.4K

192K
128
24.576M
12.288M
192K

when i hardware-bypass the ADAU1710 by connecting the MCLK/BCLK/LRCLK/DATA directly to the DAC/AMP, the speaker can output audio without any problem, so the SoC/DAC/AMP must work find.

but when not bypassing the ADAU1701, a problem comes when SoC playing 176.4K/192K sample rate audio files, speaker with no sound out, oscilloscope shows that the ADAU1701 output DATA signal is very strange, it's a constant number of 2 times the LRCLK, that's 352.8K/384K.

compare to the playing of 44.1K/48K/88.2K/96K audio file, the whole system works fine, the ADAU1701 output signals are all very good, DATA is a TRUE audio data signal, NOT a constant number, speaker output normal sound.

below is my hardware setting and tool config:

1. I have already changed the sample rate of SigmaStudio setting to 192KHz as "FAQ: How do I change the sample rate of my SigmaStudio system?" showing.

2. Hardware setting the PLL_MODE0 and PLL_MODE1 to 1 and 1 as 512xFs, according to the "SETTING MASTER CLOCK/PLL MODE" chapter of ADAU1701's datasheet P18. and will NOT change at all.

3. ADAU1701 is NOT using external crystal oscillator to generate the MCLK, but using the SoC output MCLK to instead, this MCLK signal connects to the DAC/AMP at the same time.

4. I monitor the ADAU1701 output signals, as table below:

ADAU1701 0x081C/0x081E register setting
ADAU1701 output signal
speaker output

SoC Playing File
0x081C SR1:0
0x081E OBF1:0
0x081E OLF1:0
MCLK
BCLK
LRCLK
DATA

44.1K
2x(512 instructions)
internal clock/8
internal clock/512
11.2896M
2.8224M
44.1K
normal data signal
sounds OK

48K
2x(512 instructions)
internal clock/8
internal clock/512
12.288M
3.072M
48K
normal data signal
sounds OK

88.2K
2x(512 instructions)
internal clock/8
internal clock/512
22.5792M
5.6448M
88.2K
normal data signal
sounds OK

96K
2x(512 instructions)
internal clock/8
internal clock/512
24.576M
6.144M
96K
normal data signal
sounds OK

176.4K
4x(256 instructions)
internal clock/4
internal clock/256
22.5792M
11.2896M
176.4K
352.8KHz
NO sound

192K
4x(256 instructions)
internal clock/4
internal clock/256
24.576M
12.288M
192K
384KHz
NO sound

i also try the other config of "0x081E OBF1:0" and "0x081E OLF1:0", the DATA always 2 times the LRCLK.

even when i set the SoC to output 176.4Kx64Fs = 11.2896M or 192Kx64Fz = 12.288M MCLK, the DATA still always 2 times the LRCLK.

i don't understand why and how the DATA signal becomes this 2 times the LRCLK value, or where i make a wrong config, may somebody help me?

thanks.

Audio Signal Processors

SigmaDSP Audio Processors

adau1701