Using external spdif tranceivers with ADAU1452
Hello,
My questions pertains to clock connections on the ADAU1452 when using external spdif transceivers.
My design requires 2 spdif inputs and outputs to be processed by the ADAU1452.
I have elected to use 2 WM8804 Wolfson transceivers which provide I2S output, so no need to use dsp's onboard spdif I/O. For the moment I am assuming 44.1/48kHz everywhere.
The dsp is using a 12.288MHz crystal, with XTALOUT pin going into an 8-output clock buffer. I am clocking the spdif ICs from the clock buffer, so everything is synchronized to crystal.
The I2S out of each spdif IC goes into its own SDATA_IN on the dsp. The dsp will then slave from BCLK/LRCLK of the spdif IC.
Question is, to what clock domain do I connect the output side of the dsp when sending its SDAT_OUT back to the spdif IC? I presume it needs to clock from the same source. So is it OK to connect the input-side clock domain on the dsp to the output-side clock domain?
Would you advise buffering BCLK and LRCLK from the spdif IC so that each clock domain on the dsp is driven form it's own low-z source?
Thanks for any advice you can offer me.
Audio Signal Processors
adau1452
SigmaDSP Audio Processors
Hi Chuck,
It should be fine to connect the BCLK_INx & LRCLK_INx pins together with the BCLK_OUTx & LRCLK_OUTx with both serial ports configured as slaves to the WM8804. The WM8804 seems to only provide one set of BCLK/LRCLK pins for the digital input and output. It might make sense to include source series terminating resistors on the WM8804 side.
I also see that the WM8804 can run in slave mode. If the sample rate is known and fixed, then you could also run the ADAU1452 as an I2S master on both the inputs and outputs, and probably get away with connecting only one LRCLKx and BCLKx pin to the WM8804, as long as both input and output serial ports are connected to the same ADAU1452 internal clock generator sources. With this configuration, the LRCLKs and BCLKs on the serial port inputs and outputs pins will be phase-aligned (i.e. identical clock signals).
If the WM8804 did operate with it's own separate clock source not synchronous to the ADAU1452, you could still resolve this by using a pair of ASRCs on the input and output side, and then process the audio with the DSP's own master sample rate clock source. The tradeoff here is that using the ASRCs would slightly increase the DVDD power consumption in your design. (If you are not using the ASRCs you can shut off the power in the Power Enable 0 register to reduce the DVDD power consumption further)
-JT
John,
Good to know the clock domains can be ganged. I've done it before but always wondered if it was good practice and feared some lurking issues may come up down the road.
Considered slaving the WM8804 as well. I elected to make them masters only because the ADCs and DAC are masters as well. Seemed it would be a simpler implementation and less confusing if I stuck to one paradigm unless there was a compelling reason not to.
The ASRC comments are appreciated as well. If I understand the WM8804 correctly, it will deliver I2S synchronous to the master clock, but I was concerned on that point since it is recommended to use the ASRC when using the spdif in/out pins on the Sigma. Perhaps it is a plus that needing to have 2 external spdif channels may eliminate the need for the ASRC and simplify the Sigma design.
I will heed your advice on series resistors as I have elsewhere in the design.
Thanks so much for the prompt reply. This will put me at ease about the design going forward.
chas
Hi John,
I have some follow-up questions on the spdif to I2S issue above.
To catch you up, I have my WM8804 transceivers interfaced to the 1452's Serin2 and Serin3 ports and routed through the ASRCs. The input ASRCs are configured to get signal from their respective serdata input pins, and output to dsp core at Fs=48k. Once inside the core the signal is routed to one of the other I2S outputs.
Using a standalone consumer spdif converter with analog in and 48k spdif out, I can go into the 8804 and through my dsp no problem.
However, using the spdif out from a sony BD player with a standard audio CD, I am getting a bit of noise.
Examining the I2S signal out of the 8804 triggered from 48k LRCLK, I notice that the standalone converter is operating 24-bit. But the BD player spdif out appears to operating 48/16bit. I have made sure the settings on the player are compatible with 2ch pcm stereo and not dolby or dts. (Seems odd that the spdif out for CD source is 48k, but I presume they are using an ASRC to standardize their spdif spec.... but nothing published that I can find on this.)
Cirrus has given me some assurance that I have the receiver of the 8804 configured correctly and that its I2S signal is what it should be.
Nonetheless, we would like our product to be able to handle this situation. So in trying to sort out whether I have a clocking issue or a bit rate issue, here are my questions.
How does the 1452 handle a 16bit I2S input when configured for 24bit? Will I need to detect the word-length from the transceiver and modify the serial data register setting to accommodate changing bit rates? Should I be using flex TDM to handle this situation, or is that more for accommodating channel count?
Appreciate any help you can offer.
thanks,
chuck
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