Clocks for ADAU1701 and Codec CS4272
Hi,
when the ADAU1701 is confugured as a master, getting its MCLK=12MHz from OSCO and MCLKI there are 2 possibilities in the datasheet to get the clocks to the codec CS4272. First is to use an additional buffer and get MCLK from OSCI. The second preferred option is to use MP11 as output clock divided from internal core clock (datasheet page 18).
My question is how to set the clocks when using I2S between DSP and Codec?
When using BITCLK=12MHz with a divider of 4 from ADAU1701, this can be directly connected to the MCLK_In of the CS4272. The Codec then gnerates its LRCLK=48kHz and BITCLK=3MHz . This has to be connected back to the input MP4 and MP5 of the ADAU1701, because the Serial in is always confugured as a slave.
The Sdata in is definately referred to 3MHz, but I am not sure, if the ADAU1701 Sdata_out is refererred to 3MHz or the 12MHz? Can somebody explain? How can I use the buffered output BITCLK=MP11 else as a Master clock for the system?
Regards and thanks in advance
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hi Johannes,
The divide down value is based on the internal core clock freqency of 49.152 MHz, not the 12.288 MHz MCLK input. A divide by 16 should generate 3 MHz clock (49.152 MHz/16 = 3.072 MHz).
Based on the ability to use OUTPUT_BCLK as a master clock, and the datasheet recommendation for connecting the input/output LRCKs and BCLKs together, I would think the CS4272 serial ports can be configured as a I2S slave if you want to use the "MP11=BCLKOUT" master clock option in the system.
-JT
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