cascading 2 1445 dsps
Hello,
My application requires daisy-chaining two ADA1445 dsps. I'm using 4 ADAU1974 ADCs for input, and a single ADAU1966 DAC for output.
I am connecting the serial data outs from the ADCs straight into dsp1, then out of dsp1 directly into the same-numbered serial inputs of dsp2. Then the same-numbered serial outs from dsp2 go directly into the DAC. All are operating at 24-bit, 48k off the same buffered 12.288MHz master clock.. nothing fancy.
Building off a previous design with a single dsp, I am slaving the 1445's off the ADCs and DAC. Clock domains are all connected from each codec to it's own domain, and the domains are connected to both dsps.
My questions concerns clock domain assignments. For the dsp1 inputs, I'm using domains 3, 4, 6, 7; for the dsp2 outputs I'm using domain 5. Simple enough. But now I'm wondering how best to assign clock domains to the output of dsp1 and the input of dsp 2.
Is there any reason I can't assign CD5 to the output of dsp1 and dsp2 at the same time, while also assigning 3,4,6,7 to the inputs of dsp2? Seems to me since all clocks ultimately originate from the same source, there should be no issues. But I seem to be having some problems getting audio to pass on some channels.
Please advise on best clock domain assignment strategy for this application. Or, perhaps better in this case to use one dsp as master, and slave codecs and second dsp?
any help appreciated in advance.
Audio Products
Audio D/A Converters
adau1966
Hello Chuck,
Can you explain the noise issues you are seeing? Are you hearing occasional clicks/pops, significant noise, or no audio passing at all on some channels? I would not think there should be any need for sample rate conversion since they share the same 12.288 MHz master clock.
It might make more sense to have one ADAU1445 act as the master in the system. The ADAU1445 offers a buffered digital copy of it's clock input CLKOUT which can be used as a master clock source for the other DSP or ADCs/DACs. Under such a configuration the ADCs and DACs can operate in slave mode. The master ADAU1445 can then generate the necessary master I2S clocks for all other ICs in the system.
Perhaps a block diagram of your system might help to understand what is going on here? It looks like it can work, but I just want to make sure I understand the system interconnects:
4 x AD1974 ADCs (8xI2S/16 channels) connected (as master) to ADAU1445 #1 with Clock Domains 3, 4, 6, 7 (as slaves). [i.e. 4 x ABCLKs/ALRCLKs connected to BCLK3/LRCLK3, BCLK4/LRCLK4, BCLK6/LRCLK6, BCLK7/LRCLK7]
ADAU1445 #1 8 x I2S outputs connected to ADAU1445 #2 inputs, both DSPs connected using LRCLK5/BCLK5 clock domain as slave to the master ADAU1966 DBCLK/DLRCLK (?)
ADAU1445 #2 (8xI2S/16 channels) connected to ADAU1966 with LRCLK5/BCLK5 (slave) clock domain
Given the fact the ICs share the same master clock, can you try different configurations with a separate master I2S clock between DSPs? For example, use output clock domain BCLK9/LRCLK9 on DSP #1 connected to an input clock domain BCLK0/LRCLK0 on DSP #2, and derive all DSP-to-DSP serial data pins as slaves to each of those TX/RX clock domains.
-JT
John,
My bad on not seeing your reply until now. I think I may have overlooked the auto-reply email that was sent when you posted. The email I sent to Alan is an updated version of the same problem I posted.
To your question in the post, your re-statement of the device connections and clock domains is correct:
I did also try alternative clock domain connections between dsp's as you suggested. I connected domain 3 to domain 8 on DSP1 and assigned domain 8 to the outputs so that the sdata out of DSP1 was using a clock referenced to the ADCs. I then connected domains 5 & 8 together on DSP2, assigning 5 to input and 8 to output, with the DAC as the clock domain source. This alternative connection did not eliminate the data interruption.
The serial data stream looks normal for about 100-200ms then drops out for 10-20ms and repeats. Sonically, with a 1kHz signal passing through, it beeps very much like a truck's back-up warning alarm. I see clean sine waves and good serial data during the on phase, and a 0V straight line during the off phase.
You had mentioned using DSP#1 as a master and the ADCs and DAC as slaves. If that is the case, do the clock domains on the converters need to be connected?? Or will the serial data be able to sync up OK using the converters' own PLLs? My master clock is buffered and distributed to all devices, so they should all be in sync.
I thought that if I used DSP#1 as master that I'd then have to connect clock domain 0 to sdata0's ADC, clock domain 1 to sdata1's ADC, etc. If this is the case, it will require reconfiguring all my clock domains on my hardware... which I'd like to avoid if possible.
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Thank you,
EZ Admin
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