Readback timing for ADAU1701

I am trying to optimize reading data from ADAU1701 using readback cell.

For this purpose I scoped the command sent from the SigmaStudio to dsp at the readback cell reading.

Here is the graph:

1 - Read Init (writing Data capture register address and a program step to capture data at.

2 - Read Request - writing Data capture register address.

3 - Read result - actual data reading.

What puzzles me are the delays.

4 - delay between Read Init and Read Request.

As far as I understand, with hardware capture registers it's necessary to wait until program reaches the certain step and captures data

to the capture register.

The delay at the graph above is about 400 uS. Is it necessary to have such a delay ?

At claimed 50 MIPS required delay seems to be a lot smaller.

5 - delay between Read Request and read Result. It's also about 400 uS.

I don't see a reason for this delay. Is it necessary ? And if yes, how long?

I have very tough timing constraints in my design, so clarification of this questions is important.

Thank you.

Gennady

Audio Signal Processors

SigmaDSP Audio Processors

adau1701