ADAU1442 sample rate converter and input jitter
Hi all,
I am designing a system using the ADAU1442, which I need to interface with sereval SPDIF receivers. To maximize performance, I want to implement a jitter attenuator on the I2S signals before they enter the ADAU1442.
In order to reduce the jitter, should I only 'clean' the BLCK signal, or also the LRCLK signal or perhaps both of these signals comming from the SPDIF receiver?
Thanks and kind regards,
Alex
Audio Signal Processors
adau1442
SigmaDSP Audio Processors
Anyone?
Hi Alex,
In my understanding, since the serial port uses a few samples' worth of time to convert the input from serial data to a parallel word, the jitter on individual bits (or BCLK jitter) is pretty irrelevant. The major cause of noise/distortion from external sources would be the jitter on entire frames, which is determined by the LRCLK signal.
Also, the ASRCs will do a lot of the "cleaning" for you, I think. They take an asynchronous input and re-time, or re-synchronize it to an internal reference clock.
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