AD1937 input into ADAU1442?

Hi Dave,

This is my own board, its a single channel input as this is part of an active loudspeaker.

The problem i have is I'm not sure about the other information your asking as I'm a passive crossover guy and this is all new to me. I have been working with Brett and Coleman

Hi Dave

They have the schematic, my sigma file is nothing more than the input and output blocks, configuration is what ever sigmastudio defaults to as a new project.

Im happy to send the schematic to you if you need it, basically this is the first steps after building the board and getting the various input and output sections working correctly

Graeme

Hi Dave,

Its heading your way

Graeme

Hello Graeme,

Sorry to hear about your problems. I could use a little more info. What evaluation boards are you using? If it is your own hardware then I could use the schematic. (If you do not want to post it on an open forum then I can setup a private message for you). I also would like to know more about how you are intending on transmitting the signal? How many channels? Are you using TDM4? or TDM8? It I2S? Sample Rate? Who is the master? What clock signals are you sending? What are the register settings for the AD1937? If you are using Sigma Studio then the project file would be helpful.

Thanks,

Dave T

Hello gr4eme,

Have you sent them your schematic and or your SigmaStudio project file? That would be a good place to start.

If you have not then can you send those things over to me?

Thanks,

Dave T

Hello Graeme,

I think it is faster for you to send the schematic directly to me. Sorry for the extra trouble.

david.thibodeau "at" analog.com (will need a bit of editing...)

Thanks,

Dave T

Hi Graeme,

It would be helpful to know which device is the slave and which is the master, as well as what channel count, MSB position, are LRCLK/BCLK signal properties are used in the I2S/TDM bus. With that information, I could generate a SigmaStudio project for you with the appropriate serial port and routing matrix configuration registers set correctly.

Hi Yagami,

I believe i have the 1937 set as master for ADC and its running in standalone mode. I have attached the schematic for the 1937 and 1442

Hi Dave,

SDA is high you can just about make out the 3v3 label under the arrow there is a clock on the MCKLI pin and its functioning correctly.

The PCB is a 4 layer as specified and confirmed by Brett and Coleman

Any clues how to get the input functioning would really be helpful as i can't do anything else until i ca get an input into the 1442

Graeme

Hi Dave,

Thats not good news i don't see anyway i can change the clock inputs on the finished PCB without re designing and having new boards made.

Would it be better to make the 1937 run in slave mode? this is some what do able on the finished board or would i still need to change the clocks?

Graeme

Thanks Dave,

The slave mode was a real easy fix as its just a case of removing the solder between the 2 pins on the 1937.

Its frustrating that this was missed under the schematic review but I guess thats all part of the micro electronics life, I'm learning this on my first ever project lol

Do i need to move both LRCLK0 and BCLK0 to LRCLK3 and BCLK3 to solve this issue?

Graeme

Hello Graeme,

You do have it setup to go into Standalone mode. However, I cannot tell exactly which mode you are setting it into. The only choice you have is for master or slave but the schematic has an arrow from the SDA pin and I have no idea where it is going to. If the SDA pin is low then the part will be in slave mode. If it is high then it will be in master mode.

The MCLKI pin label has a question mark in the name. You will need to have 12.288MHZ fed to that pin for the part to work in standalone mode.

Standalone mode will be stereo I2S so therefore channels 1 & 2 data will appear on ASDATA1 pin and channels 3 & 4 will be on the ASDATA2 pin.

The DAC will also be configured to I2S format so you will need to send the data to pins DSDATA1 thru DSDATA4 pins two channels each. So if you are not using all the channels then you do not have to send anything but we recommend that you ground the unused DSDATA inputs to prevent and garbage or crosstalk from coming into the DAC inputs. Since you are not using the ASDATA2 then leaving it floating is fine.

I see you are using clock domains 0 and 1 on the ADAU1442. I think that will be fine since you are not doing any re-clocking to other domains nor using sample rate converters but Yogami, (Brett), can comment more on that.

I see you do have some series terminating resistors on the clock lines. That is good and should be fine for this simple arrangement of the clock transmission lines. If you have to go to other places with the clocks then you may want to have other options. In addition, you will need to have at least one ground plane on your PCB. You will need a minimum of four layers in your design and the inner layers will have to be power and ground planes. Should you need more layers then the layer stackup will be very important and need to be thought out. There are lots of options so I will not go into it here. The 33-ohm value is a good starting point but the optimal value should be obtained by using signal integrity simulation program once the PCB has been designed. This way you would use the actual PCB details to figure out what the value of these resistors should be.

So it is looking like you are in pretty good shape. Just let us know what the SDA line on the AD1937 is set for so we can determine if the part is in master or slave mode. Then Yogami can help you further.

Thanks,

Dave T

Hello Graeme,

OK, then you are running in Master mode. The sample rate will be 48K. It would be best to use the ADC clocks to drive the ADAU1442 so clock domain 1 would be what you use in the Sigma DSP.

Now, in looking more closely at the ADAU1442, you will need to do one of two things in the hardware. Either move the ADC clocks to one of the assignable input/output clock domains. That would be clocks 3-8, just one of them not all of them. An alternative is to move the DAC clocks over to one of the input/output, or just output, domains. Clock 9-11 are output only clock domains.

The problem is that the serial output ports can only be clocked out using domains 3-11 and the input serial ports can only use 0-8. Domains 3-8 can be used for either or both. So you can move the ADC to clock 3 and use it for both the serial input and output ports or continue to use clock 1 for the ADC data and move the DAC clocks over to an output domain. What ever is easiest to do on the PCB.

Let us know which one you did. I will not be able to setup a SigmaStudio project for you until later and I would guess that Brett will not be able to for a little while. To speed things up a bit, make the hardware changes then send me the project you currently have. I can take a quick look at it sooner and offer some suggestions but it will be a while before I could bring an eval board into the lab and supply a tested project.

Thanks,

Dave T

I will check on a work around. No, slave mode will not help. I will need a little time to look into this. I will get back to you with more info as soon as I can.

Thanks for your patience,

Dave T.

Can some one confirm the above question as if this is the case i would like to get boards on order today

Many thanks

Graeme

Hello Graeme,

Try out this project. I was having trouble getting the input to be clean but I am not sure it is the fault of the project setup. So try this out and let me know what you find. I can get back to this in the morning.

Use your current hook up of the clocks on the PCB. Do not make any changes. I am trying to make this work.

Thanks,

Dave T

Hi Dave,

I set up my board with a differential input of 1KHz on the input stage, i can track this all the way to the input pins at 1.17V AC and see a clean sign wave, with the program loaded I'm not seeing 1KHz on the output, I'm seeing a mixture of noise between 2k and 10k and an output voltage of 0.6V, I swapped in the signal generator on the output of the other dac and get a perfect 1V at the set frequency with no noise

Graeme

Hi Dave,

Yes both the 1442 and 1937 are running from an abracon oscillator, I will fire up the soldering iron and see if i can get the 1937 in slave, as you can see from the berbers the link is under the pins lol I'm hoping i can clear the solder and cut that link to the pin next to it.

Give me an hour and i will get back to you

Graeme

This looks to be working

Graeme

Hello Graeme,

That is good actually. I was getting the same thing here but I was just not sure if it was my setup or not. I thought about this some over the evening and driving in this morning. So I went into the lab and the problem is with the timing of when the clocks get turned around to drive the DAC when using the ADC clocks as master clocks. I changed the AD1937 to run as a slave in standalone mode by changing the SDA pin to ground. Then on the ADAU1442 I made both the clock0 and clock1 domains masters. I changed the clock source to internal master and made the DSP start pulse be the internal 48K clocks. Then I got nice clean data in both directions and it looked good on the scope as well.

I attached the edited project so you can see the settings. The DSP Start Pulse select is on the DSP Register Modes 1 page of the register control window.

The difficulty with your setup has to do with how the clock domains can be routed internally. Clock pins 0-2 can only route to the serial input ports. Clock pins 3-8 can route to serial input or output ports and clock pins 9-11 can only route to the serial output ports. Then to make matters worse the serial input ports are associated with the clock domain. So since you are bringing in the ADC on clock pins 1 and the data is coming into serial port 0 makes it a little tricky. Then the internal clock domains 0-8 for the serial output maps domains 3-8 to clock pins 3-8 but domains 0-2 map to clock pins 9-11. So the serial output ports 0 and 1 that you are using will output their clocks on clock 9 and 10.

Note: when I say "clock pins", I mean the pin names not the actual pin numbers. I use the words "clock pins" to differentiate between the internal clock domain numbers and the pin names.

So the solution is to just make the ADAU1442 the master of the universe and so all the clocks will be synchronous.

One other important thing. I assume the master clock for both parts are coming from the same clock source? They need to be on the same clock. If they each have their own crystal then that will be a problem. If this is a problem then I can help you work out that problem.

Let me know how this all works out.

Thanks,

Dave T