SigmaStudio probe : FIR phase error ? (ADAU1452)

oops, forgot to mention that the compiler output seems not to reflect the exact workload of the CPU core, as it should need around 250+ int cycles, right ?

can you please also confirm if the FIR coeficient are converted from real to 8_24, then we might have interrest to normalize above 1 to use the full 32 bits capabilities of the ALU

Hello maxidcx,

To investigate the phase issue I built a FIR filter with a known response and plotted it:

This FIR kernel has all zero coefficients except a "1" in the middle. Thus it's no surprise that it has unity gain, flat frequency response and a constantly increasing phase lag. It's functionally identical to the delay just below it, and the two have identical gain and phase plots:

Knowing the expected phase response, I can see two issues with the Stimulus-Probe phase plot in SigmaStudio:

The phase axis is shown as "radians" but its actually in degrees. The filter has a 500-sample group delay, which works out to 10.4 mS at a 48K sample rate. This produces a frequency-dependent phase shift -- for example, at 1000 Hz, the delay amounts to 10.4 complete cycles of phase shift, equivalent to 3750 degrees or 65 radians. The graph shows about 3750, so it must be in degrees. That's about 58 times higher than the radian figure.

Once the phase lag exceeds 6018 degrees, something overflows and you get the cyclic results shown. The actual phase shift, on the other hand, just keeps increasing.

So apparently something is wrong with the phase display in this case. I don't suspect it affects the actual FIR performance, because the coefficients you worked out go into the DSP while the Stimulus-Probe response is figured separately. Neither hardware nor compiling is needed to use Stimulus-Probe. Also, I tried the same experiment above with a ADAU1452 and a AD1940, and received the same results even though the chips use different compilers.

Best regards,

Bob

Hi maxidcx,

Within a FIR filter, SigmaDSPs can handle the result of multiplying two full-scale numbers. This was demonstrated for a ADAU1701 at https://ez.analog.com/thread/36478, it also works for the ADAU1452. Below the slow, full scale (127.9 peak) sine wave drives a FIR differentiator with two maximum value, opposite polarity taps. This produces numbers approaching +/- 16384 that nearly cancel out, leaving a small clean sine wave as the FIR output.

Thus theoretically, you can go larger on your FIR coefficients. ADI put all that headroom in for a reason, however. Audio has a way of reaching unexpected peaks. The fixed-point SigmaDSP handles this simply by leaving lots of headroom. With 24 bits after the binary point, there's hardly any reason to encroach upon those bits before.

Best regards.

Bob

Hi, maxidcx.

I'm using chip ADAU 1701, fs=48000.

Sorry, I am a newbie in filter designing.

I would like to design an IIR Notch filter at 1kHz. I used "Fixed-Point Table Generator" to get the coefficients.

Then, I feed that IIR output into another FIR filter to correct the phase shift. I'm using 'rephase' to design the FIR filter and get 128 taps of impulse response and then fill in the FIR filter in SigmaStudio.

Below is capture screen scope IIR:

IIR filter generates some phase shift around 1kHz. (Q=1, Butterworth, cutoff at 1kHz, fs_1=850, fs_2=1150).

But I could not get the expected result in Simulation Probe. I guess the output should be a linear line 0 degree.

This is the screen of phase display:

Am I using wrong method to get the FIR coeff? Or the phase display is incorrect?

Hope to hear from you soon.

Thanks alot,

JCB

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