how is the function of the i2s digital out

Hello hubijo,

Here's the settings I have used to transmit I2S audio from a -1701:

The MP pins are set up for Output Sdata 0 and 1 at MP6 and MP7. MP10 and MP11 provide your I2S clock outputs.

The Frame Sync (LRCLK) runs at the internal clock (the MIPS rate) divided by1024, which is the same as your 44.1K or 48KHz core sample rate. The Bit Clock (BCLK) runs at MIPS/16, or 64 times faster than LRCLK. This actually allows for 32 bits each per left and right samples; the unused bits are zeroed on this end and ignored at the receive end. Delaying the MSB by one bit is the most commonly used setting.

Best regards,

Bob

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