Sigma EVAL-ADAU1761Z  to  1761 application borad compiler 2 times  to sound

Hi Meican,

I'm not sure how we can help you here. Do you have a specific question about using the ADAU1761?

Best regards,

Coleman

Hi Meican,

Perhaps your USBi is losing some data transfer from your PC. Be sure to plug it into a USB 2.0 port (not a 3.0 port which has a blue colored jack). Also try another USB cable, short ones work best.

Best regards,

Bob

Hi Coleman,

My 1761 application is as below: Analog L/R in and Bluetooth I2S in.

cid:image002.jpg@01CECA7F.9342F7E0

My question is :

1. Analog should work well by 22.5792MHz MCLK , can get 48k Fs in 1761 ?

2. In I2S mode , Bluetooth is master, and out 44.1k Fs , 1761 is slave , by OSC 22.5792MHz ( not from Bluetooth), Can DSP work properly? I am thinking I2S singnal is not sync. With 22.5792 MCLK in this situation.

3. In I2S mode , can we use 8MHz MCLK from Bluetooth ?

4. Important: How DSP lock external MCLK ? and when ? powers on DSP , once MCLK pin capture clock then ?? ms later , DSP lock the input clock from MCLP pin automatically ?

5. Control and download by EVAL-ADAU1761Z using I2C, my 1761 board works well . but download this function default_download_IC_1() by MCU by I2C. the board does not work. I am sure the I2C is fine. Since I can control single commond by MCU I2C like sending ( 0x70, 0x00,0x08,0x00,0x80,0x00,0x00 ) , DSP is controlled.

Here also I read 0x4002---PLL lock bit , seems no locked , so I asked , how does the DSP lock the MCLK clock?

6. If PLL is bypass, then no need PLL lock operation ( in software) ?

Meican.Wu (吴美灿）

Electronic Engineer Department

cid:image001.jpg@01CC76D9.D5149B20

Tymphany Industrial Area,

Xin Lian Village, XinXu Town,

HuiYang District, Huizhou,

Guang Dong, P.R.C. 516223

phone. +86.752.3059.888 ext 858

18607521910

fax. +86.752.353.0222

url. www.tymphany.com<http://www.tymphany.com/>;

1. If you use a 29.5792 MHz input clock, you'll want to set the PLL pre-divider (X) to 2 or 4. Let's use X=2 in this example. 29.5792 MHz / 2 = 14.7896 MHz. Since you want a 48 kHz output, the core clock should be 49.152 MHz. 49.152 MHz / 14.7896 MHz = 61440/18487, or 3 + 5979/18487. Unfortunately, this is not a nice, simple fraction. However, the fractional PLL can handle it, because it allows for 16-bit numerator and denominator settings. So, your PLL settings should be X=2, R=3, N=5979, M=18487.

2. If you want to use a signal source at 44.1 kHz, then you'll either need an ASRC (asynchronous sample rate converter), or you'll need to change the settings of the fractional PLL again to accept the input.

3. Again, if the master clock frequency changes, you'll need to reset the fractional PLL settings for this new frequency.

4. The PLL will attempt to lock to the MCLK signal after you program the corresponding PLL control register. It may take several ms (greater than 10 ms sometimes) to lock to the external clock, depending on the settings.

5. Are you writing all 6 bytes of the PLL register? That might potentially be the cause of the problem.

6. If the PLL is bypassed, you need to feed the clock directly to the device at the correct frequency. The PLL does not need to lock in this case.

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

Thank you,
EZ Admin