MCLKI with I2S in ADAU1701

I was looking to add SPDIF input to a project i was working on using the 1701 and stumbled across this application note

http://www.analog.com/static/imported-files/circuit_notes/CN0219.pdf

problem is that once you go digital the clocks must be the master clock from the spdif so you end up needing to switch the clock without a glitch and this is where my original design started to get crazy complicated so much so that im now working on redesigning based around the ADAU144x family

Hope this helps

Hi Ari,

The ADAU1701 does require an MCLK, and the MCLK and BCLK/LRCLK must be synchronous, but not necessarily phase aligned. If there are crossing edges between MCLK and BCLK, there will be some unpredictable audio artifact during the crossing event, until the edges become valid again.

We do have parts with ports which will run asynchronously, please look at the ADAU1442. Do you need an ADC or DAC as well? The AD193x family of codecs/ADCs/DACs have a PLL which will run from LRCLK, and these parts will generate an MCLK for other devices in the system.

Best regards,
Coleman

Hello ColemanR,

We have an existing design with ADAU1701 and as we are spinning out a new PCB for that we try to incorporate support for BT module also. So switching to another family would be too much work right now.

BT module vendor said they can create FW which sets BT bit clock to 3.072MHz (48 kHz * 2 channels * 32 bits/channel); they can't go higher than that. Would it work if that same bit clock is used for I2S bit clock and as ADAU1701 master clock input?

Thanks,

Ari

Hi Ari,

Connecting the 3.072 MHz clock to both BCLK and MCLK would be the best solution. In this configuration, please set the PLL to 64 × fs by setting PLL_MODE0 (pin 38) and PLL_MODE1 (pin 39) both to GND, and also take into account the increased amount of time required for PLL lock listed in Table 11 of the datasheet.

Best regards,
Coleman

Hi Ari,

I have the same issue as you had with the BT-module.

My BT-module supplier can also output 3.072MHz on the BCLK pin and I could use that as MCLK input for my ADAU1702.

But, the BT-module supplier says that BCLK=3.072MHz only when the A2DP-source (media player in the phone) runs with a sample rate of 48kHz. If the source has a sample rate of 44.1kHz then BCLK will be 2.8224MHz instead. In that situation BCLK will not be a valid MCLK input to ADAU1702 - or?

How did you solve this?

Your input in this would be highly appreciated!

Thanks and best regards

Markus

Hi Markus,

In the ADAU1702 datasheet, we do not appear to explicitly say that the ADAU170x will operate using 2.8224 MHz (Fs = 44.1 kHz). Table 10 shows the power-up times for PLL lock at various MCLK frequencies, and 2.8224 MHz is not on the list with 3.072 MHz. The spec table shows a +/- 20% window for MCLK functionality, and this is only ~8% lower. I am confident that you will have a robust design in this mode.

Best regards,

Coleman

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