Clock distribution from ADAU1701 to external ADC/DAC
Hello,
I would like to run the ADAU1701 with external ADC's and DAC's, maximum is 4 ADC and 4 DAC. I know for best audio result the clock has to be synchronized to all ADC and DAC . What is the best way to distribute the clock signal? Use special clock distribution IC? Or maybe simple CMOS drivers enough for this "low" sample rates (maximum 96kHz)? Or any other solution? Thank you in advance!
Thomas
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hi Thomas,
When you say 4 ADC and 4 DAC, do you mean channels, or ICs?
If you mean just 4 channels of each (existing in one or two ICs), then it is fine to just run the traces from the ADAU1701 directly to the ADC/DAC chip and put the ADAU1701 in master mode on its serial port. It has enough drive strength to comfortably drive two slave devices, provided there is a good PCB design.
However, if you mean that you could interface the ADAU1701 to potentially up to 8 external ICs, then you'll definitely need CMOS buffers on the bit clock signals. The LRCLK signals might be fine without buffering since they're quite low freqeuency (only 96 kHz in your case). For the master clock signal, which is going to be over 10 MHz, it would make sense to use a clock distribution IC (for example, the ON PCS2P2309NZ).
We don't really have a reference design for this because it's uncommon to see more than a few codecs in the system. If you want to start doing your design and post questions here when you have them, I would be happy to review your design and answer your questions.
Hi Brett,
thank you so far, that helps a lot. I want indeed use a maximum of 8 external IC's. The ON Semi IC seems to be a good choice, what is the maximum recommended length for the clock signals? (I know, as short as possible )
Thomas
Hi Thomas,
You are correct that shorter traces are better, and there are other guidelines you can follow to have a successful design. First, I hope that you are able to design a 4-layer board. The second layer should be a single solid ground plane; I do not recommend splitting your ground into separate analog and digital grounds. The third layer should be a single solid power supply layer; choose the power rail that is used most widely across the board and make this into a plane. In the clock and data lines, some simple line termination in the form of a series resistor will make a big difference in your signal integrity and EMI radiation; I would start with a value of 33.2 ohms and see how your signal look once the board has been manufactured. Please let me know if you have any questions regarding these guidelines.
Best regards,
Coleman
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