about usb_clk in EVAL-ADAU1701MINIZ
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We have a EVAL-ADAU1701MINIZ board, when we check the schematic drawing, we find that usb_clk is a one-end net. It is pin 2 of J8. Where does it go?
THanks.
BR/Jackie
That signal was originally intended for being able to generate a master clock inside the USB board and use that to clock the evaluation board. However, we have not implemented this functionality yet in the board's firmware, so we have not connected this signal to anything on our evaluation boards.
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