ADAU144x XTALI to CLKOUT Jitter
With a scope set to trigger off of the clock input to the XTALI pin and simultaneously looking at the CLKOUT pin, I observe about 5nSec of jitter over time with between the two clock signals. This is true of a couple of in house designs. The PLL components are as close as possible to the chip. I also see about this same amount of jitter when I look at the ADAU144x evaluation board.
Is this to be expected and if so is there a specification for this?
I note that if I touch the PLL node with a scope the jitter goes away. Are there other recommended PLL values?
Thanks
Hi,
The jitter between XTALI and CLKOUT is not characterized in our tests, so I don't have an expected range for that value. The fact that you can vary the jitter by "interfering" with the PLL loop filter is surprising. Perhaps this is adding additional bypassing to the PVDD supply? Maybe it would be worth it to put an additional 10 nF or smaller bypass cap between PVDD and GND to see if this has a positive impact on jitter.
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