ADAU1442 44.1k input / 96k core Fs? Confused about clocking

Say, i'm using a 24.576MHz crystal for the DSP clock, and using 96KHz as an internal sampling rate.

If i have a stereo signal coming in through Sdata0 which is sampled at 44.1KHz, and that's routed through an ASRC, all should be fine and dandy, right?

Absolutely

Or, as a more general question, can the clocks for the serial inputs be somehow "slaved" to the serial data source? Or can / do the ASRC's automatically detect the sampling rate of the incoming data stream and auto-adjust accordingly, in order to output the data at the selected core Fs?

The clock on serial data lines can be master (so it is imposed to the connected devices) or slave (the connected devices are generating the clock signal).

While you are into the ASRC conversion range (don't remember, but i'm using 192KHz for core frequency and i can happily handle 32 to 48KHz input, but i'm sure it is even more...look at the datasheet), any sampling frequency you put into, also 35.427KHz or 42.1234KHz, is converted to your core frequency.

Or, approaching this from a different angle, are the input clocks "pre-determined" in the self-boot data written into the EEPROM, or can they be altered during normal operation of the DSP?

I don't fully get this.

If you are referring to the fact that you should know previously what will be the input frequency to the ASRC and then program into the eeprom, no, you don't.

In an application, i did change the audio codec clock frequency in order to change its internal lowpass filter corner frequency (so the input bandwidth). Obviously this made also the sampling rate to vary, but this was handled flawlessly by the ASRC.

Bye

Tom

Tom, thanks a bunch for the extensive answer, it HAS helped clear some things up (that may not be as well explained in the datasheet, as they could be)

So then... In SigmaStudio, in the DSP Register Control, in the Serial I/O section, in order to allow this ASRC auto-lock flexibility, for the relevant serial inputs, in the "Master/Slave & Clock Domain (bits 13:10), am i supposed to select "Slave to Clock Domain x", or "Master - xx kHz clock"? This is what i meant by 'input clocks "pre-determined" in the self-boot data written into the EEPROM'.

Best regards,

Chris

ASRC auto-lock flexibility, for the relevant serial inputs, in the "Master/Slave & Clock Domain (bits 13:10), am i supposed to select "Slave to Clock Domain x", or "Master - xx kHz clock"? This is what i meant by 'input clocks "pre-determined" in the self-boot data written into the EEPROM'.

Ok Chris, got it.

If you are master, you impose the clock frequency, so then you have to select what is it.

In your example, you have a core frequency of 96 khz and you can be a master for a 48KHz (fcore/2) ADC.

You cannot, while in master mode, clock a peripheral at 47.12KHz, only that frequencies listed are allowed.

That's why it is a fixed value and you have to choose it.

Instead, in slave mode, you can have different devices running at different frequencies (clock domains) so they

can be any permitted in the ASRC input range....45.27khz, 66.97khz and so on.

In this case, as you see, you just select what is the domain to be slaved to the incoming clock.

More practically, let's imagine you have a system which has to handle voice limited at 8khz, low-fi music at 15khz, and hifi music at 24khz. Core frequency is 96KHz.

Instead of wasting processor cycles in filtering the various inputs, you can use the fir filter contained into the AD converters, but you will have to clock them at different frequencies in order to get your desired frequency cut.

So, you will have two different external clocks for the voice and low-fi music converters, while you can have the hifi music converter directly clocked by the dsp.

This will end up in having voice converters connected to some slave serial ports tied to, say, clock domain 0, the lowfi converters will be connected to other slave serial ports tied to clock domain 1.

You could have another external clock for the hifi music converter also, but since its sampling frequency can be generated directly by the dsp, you can then connect it to a master serial port configured for 48KHz sampling rate.

Bye

Tom

Ok, that makes a lot of sense.

A part of my "project" concerns an ADAT input, and configuring the ADAT receiver chip (Wavefront AL1402G) to recover the clock from the optical input, and that way, acting like a master clock (it outputs the clock signals).

So if my understanding's correct, as long as the DSP's serial inputs (coming from the ADAT receiver) are all slaved to the same clock domain, all should be well, right?

So if my understanding's correct, as long as the DSP's serial inputs (coming from the ADAT receiver) are all slaved to the same clock domain, all should be well, right?

Right.

All inputs belonging from the same clock source which is not generated by the dsp, are slaves and they have to be tied to the same clock domain.

I specified "the same clock source", because if you have two different ADATS, though they can have the same sampling rate, they will not be synchronized to each other, so in this case you have to use two different domains.

Thanks a bunch, finally the mists in my understanding have cleared away.

The ADAU144x datasheets could include a few quotes from your replies

Merry Christmas and a Happy New Year!

The ADAU144x datasheets could include a few quotes from your replies

Yes... If Analog would hire me to write down datasheets and examples, i'll be glad to accept!

Thanks and Merry Christmas to you!

Tom.

Thanks, drugoimir. You did a great job of answering this question while I was out of the office. I really appreciate it!