An Integrator Block for SigmaDSP

Once again, this is great work. Thanks for contributing this to the community.

good day everyone,@KJBob, @

I want to implement stand alone DSP to process integration of trapezoid rule repetitively. The firmware would be developed in the DSP's SIGMASTUDIO. Next I would read the integration output using Readback block by SPI of STM32F4 microcontroller. Readback block algorithm is ready.

For the integration of trapezoid rule,

,

where and .

lowbound,a = 1st sample, X0

upbound,b = 101th sample, Xn

intervals,n = 100

f(x) = sample(n)

Is it possible?

thanks

kal

Hello Kal,

I'm afraid it's been 45 years since my last calculus class, so the integrator that's the subject of this thread was of the simple zero-order variety. Lyon's book Understanding Digital Signal Processing shows a trapezoid-rule integrator with this formula: y(n) = 0.5 x(n) + 0.5 x(n-1) + y(n-1) Recognizing the first two terms as a moving-average FIR filter, it's easy to modify my integrator to perform the trapezoid rule:

Looking at the formula you provided, it appears you wish to calculate a definite integral of 100 intervals between 101 samples from x = a to x = b. You didn't specify the rate at which your samples arrive -- if this rate is sufficiently low, you might as well have your microcontroller perform the calculation. If on the other hand you wish to sample your input at a typical "audio" rate such as 48000 per second, you could press a SigmaDSP into this service.

The circuit shown below demonstrates an example calculation:

The top portion is a clock which counts sample intervals from 0 to 203 then resets. For the first 101 sample intervals your input signal is allowed through two scaling blocks to the 101-tap FIR filter which calculates the definite integral. After 101 intervals, comparator ABCD1 shuts off the input, while Hold1 retains the filter output at that moment. During the next 102 intervals the filter empties out to get ready for another integral, while Hold 2 latches the previous result and just before the process starts over, the GPIO signals an output pin on the DSP which you could use to trigger a SPI read from your micro (if needed). I drew up two similar versions of this project, for the ADAU1701 and the ADAU1466. Both worked about the same.

What I came up with is simply to show what you can do with these DSPs -- it may not do exactly what you need or perform it accurately enough (etc), but it does demonstrate the capability available to you. Remember that SigmaDSPs are fixed-point with 24 bits after the binary point (roughly six decimal digits), so be mindful of round-off errors. I recommend you scale the integrator's gain (time constant) according to the sort of signals you're measuring to minimize the errors. That's why I built a gain of 100 into the above example -- without it the result measured low by about 0.4%.

You can open the attached project in SIgmaStudio to examine details the screenshot doesn't show, such as the FIR coefficient table. If you have a ADAU1701MINIZ board you can run the project as well. The -1701 truncates the lowest four bits in its readback register, so for maximum precision you might wish to choose a different DSP-- although I suspect the major accuracy limitation is not reading the final result but with round-offs of much smaller numbers within the intermediate calculations.

BTW -- the legendary BrettG who years ago helped me get started with SigmaDSP, is no longer on these boards.

Best regards,

Bob

Good Day Bob,

Thanks for the fast response with detail description. What an abundant info to chew but very great info for me to kick start the idea u provide.

And It's a big loss to us for him to been away from these boards.

By the way, your input is really helpful!

Best regards,

kal