ADAU1701 - DC Bias
Thread Summary
The user asked about the DC bias in the ADAU1701's ADCs and DACs. The 1.5VDC bias ensures that audio signals can pass without distortion, as the pins cannot go below zero. Capacitive coupling is required for both input and output to block the DC component and maintain a symmetrical signal. The user confirmed that designing the circuit like the EVAL-board would achieve the desired result.AI Generated Content
Hi you all,
I think, I have not really understood some hardware details.
Please, could someone tell me, what the values DC Bias in the electrical specifications of ADAU1701s Audio ADCs and DACs exactly mean?
Thank you....
Kind regards
Rasterjannik
Audio Signal Processors
processors and dsp
SigmaDSP Audio Processors
Processors and Microcontrollers
adau1701
Hi,
The 1.5VDC bias on the ADAU1701's ADCs and DACs allow room for the bottom halves of audio waveforms to pass unimpeded, since none of these pins can go below zero (no negative supply is used). Internal circuitry holds the audio pins at approximately this DC level. Thus the user needs to capacitively (AC) couple audio into and out from the chip. AC coupling is included in its usual application circuits.
On the input side, capacitive coupling allows the chip to develop its DC bias at the input pins, in turn allowing the ADCs to center their numerical outputs at around "zero" (halfway between plus max and minus max). It appears possible to DC couple these inputs if needed (perhaps for an instrumentation application), see: https://ez.analog.com/message/42629#42629
On the output side, the specified DC bias appears superimposed upon the desired audio. Generally your external output filter (see https://ez.analog.com/message/60725#60725) would include a series cap to block this DC. All the DC blocking caps essentially form first-order highpass filters with a corner frequency of a few Hz. If inside your DSP project you find unwanted residual "DC", insert a DC block or HP filter.
Dear Robert,
thank you for your helpful reply.
As I have understood you I only have to design input and output schema in the way, the EVAL-board realizes, to enter my circuitry with a symmetrical (GND-centered) signal and get out a symmetrical signal. Is this correct? That would be easy.
sincerely
Rasterjannik
Yep, and it's just that easy.
Bob
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