ΣSigmaStudio Ask AI Русский Log in

ADAU1442 TDM4 mode and synchronization with CODECS AD1938

SigmaDSP & SigmaStudio ChrisDan Aug 9, 2012 00:00 2 replies Original on forum ↗
Subscribe
ChrisDan Question
Aug 9, 2012 00:00

Hi,

intended configuration as follows:

One ADAU1442, master, generating BCLK, LRCLK, Audio-Data communication via SDIN and SDOUT in mode TDM4.

Six AD1938 CODECS as slaves, each with own crystal 12.288 MHz, ext. synchronized by ADAU1442 (master) BCLK and LRCLK. mode TDM4.

No MCLK distribution due to EMC aspects.

Is this a working configuration ?

Kind regards

Christian

Audio Signal Processors

ad1938

adau1442

Integrated/Special Purpose A/D Converters

SigmaDSP Audio Processors

Audio CODECs

Show More

ColemanR Reply
Aug 9, 2012 00:00

Hi Christian,

I am concerned about clock synchronization in the setup as you have described it. If you are running each AD1938 from its own independent crystal, and driving each codec's LRCLK and BCLK ports from an external device, I think you will have trouble with the AD1938 staying locked - for each codec, there must be synchronicity between MCLK and the port clocks (LRCLK and BCLK). I would recommend that you use LRCLK PLL mode in each of the AD1938 codecs, remove the crystal from each AD1938 and change the loop filter as recommended in the datasheet. You will be able to run the codecs in TDM4 and LRCLK PLL slave mode with no trouble.

Alternately, you could run the AD1938 codecs in Master mode, each with a crystal, and drive your port clocks from the AD1938s to the ADAU1442. I would recommend the first scenario, since it allows you to remove the crystals from your BOM.

Best regards,

Coleman

ChrisDan Reply
Aug 10, 2012 00:00

Thanks Coleman,

it was as well my first planning to set the AD1938 PLL and Clock Control register to LRCLK input (DLRCLK or ALRCLK, regardless of which due to the parallel connection of DLRCKL and ALRCLK pins) for synchronizing with the frame clock of the ADAU1442. It's helpfull to know MCLK is not necessary and TDM4 mode will work.

A little drop of bitterness is the use of the PLL instead of a hardwired clocking, i hope this cause no trouble.

Thanks

Christian