ADAU1701 PLL Slave mode
1. May I know whether ADAU1701 can support for PLL slave mode ?
As I know that in different MCLK input need to be catered for different audio sampling rate during PLL master mode.
Our design need to support for 48KHz,44.1KHz,16KHz and 8KHZ audio sampling rate, then MCLK input have to be changed
accordingly when audio sampling rate change. The problem is our design cannot cater for so many different MCLK.
If ADAU1701 can take BCLK as reference clock during PLL slave mode then we don't need MCLK anymore.kindly refer to diagram below
2. some other supplier support master mode, without change MCLK, internal PLL can support different sampling frequency, can ADAU1701 do that as well, if not, what the recommendation to implement this requirement.
Thank you.
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hello,
The ADAU1701 can only operate at nominal sample rate, 2x sample rate, or 4x sample rate. Typically, nominal sample rate is either 48 kHz or 44.1 kHz, so the possible rates are 48 kHz, 96 kHz, 192 kHz, 44.1 kHz, 88.2 kHz, and 176.4 kHz. Running at slower rates is not possible because of the integer PLL and the limited range of operating frequencies for the audio clocks.
The ADAU1761, however, can easily support your required rates of 48 kHz,44.1 kHz, 16 kHz and 8 kHz (and many others) with a single MCLK frequency due to its more flexible clocking options.
Have you considered using the ADAU1761?
Can ADAU1701 support PLL slave mode as mentioned above which you don't need MCLK ?
(The clock will take from BCLK which generated from my system instead of MCLK)
The ADAU1701 requires an MCLK. You need to supply an MCLK signal to the MCLKI pin. It can be at any of the following rates, defined by the state of the PLL_MODE0 and PLL_MODE1 pins:
(where fS = 48 kHz or 44.1 kHz)
So, the four possible options for MCLK in a 48 / 96 / 192 kHz audio system are:
3.072 MHz (64 x 48 kHz)
12.288 MHz (256 x 48 kHz)
18.432 MHz (384 x 48 kHz)
24.576 MHz (512 x 48 kHz)
The four possible options for MCLK in a 44.1 / 88.2 / 176.4 kHz audio system are:
2.8224 MHz (64 x 44.1 kHz)
11.2896 MHz (256 x 44.1 kHz)
16.9344 MHz (384 x 44.1 kHz)
22.5792 MHz (512 x 44.1 kHz)
From Lee
Can ADAU1701 support PLL slave mode as mentioned above which you don't need MCLK ?
From Brett
The ADAU1701 requires an MCLK. You need to supply an MCLK signal to the MCLKI pin.
So, answer is no.
Mark.
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