Clock for Class D Amp

Hi Austin,

The Nyquist–Shannon sampling theorem shows that for a system with a sampling rate of 2B Hz, the highest frequency that can be represented is B Hz. From this, it follows that a SigmaDSP running at a sample rate of 48 kHz cannot generate an output signal greater than 24 kHz, and since all of the signal generators within the SigmaDSP can only be updated once per sample, there is no way to avoid this limitation. Unfortunately, I can't think of a way to generate a 700 kHz clock using the ADAU1701.

You could enable the OUTPUT_BCLK signal on MP11 and feed it into a counter.

Cheapest implementation would probably be a 74HC163 - clock it with MP11, strap the terminal count line to the parallel load line, and configure the parallel inputs to give a suitable clock divider. With OUTPUT_BCLK set to /8 (6.144MHz), dividing by 8 gives you 768KHz and dividing by 9 gives you 683KHz. If you want more accurate than that, BCLK at /2 (24.576MHz) divided by 35 gives you 702KHz, but that's a bit harder to pull off with cheap 74xx bits.

I'm using OUTPUT_BCLK in a design to feed 24.576MHz from an ADAU1701 into a pair of ADAU1592s. Couldn't be happier with it.

Thanks gmarsh!

That's a great idea. I had never thought of using an external counter to achieve this functionality. That's a good approach.

Missed something - you need to invert TC before connecting it to /PE, using a tinylogic gate or similar. Do that, tie CET/CEP high, and feed OUTPUT_BCLK into the CP pin.

If you want to do /8, feed "8" into the parallel inputs. The counter will count 8,9,10,11,12,13,14,15,8,9. Think about what comes out of the Qx pins in this scenario - Q3 will always be high, Q2 will output /8 at a 50% duty cycle, the remaining Qx will output something probably less useful.

To do /9, feed "7" into the parallel inputs. The counter will count 7,8,9...14,15,7,8,9...

Q3 will be high 8 out of 9 times, but it'll give a /9 clock. Q2 through Q0 will output garbage.

That makes things simpler. Tie /PE, /MR, CEx all high and feed OUTPUT_BCLK into CP.

You'll get OUTPUT_BCLK/8 out of Q2. (Q0=/2, Q1=/4, Q3=/16)

Hey thanks, that sounds exactly like what I need, but could you elaborate a little more? The concept and logic I get, but the setup of that chip is confusing me. I run the AD BCLK into the counter CLK and connect "Terminal Count Output" into "Parallel Enable Input" then run Q3 into the amp clock, which will give me 768KHz there? Other than the obvious power and enable pins, the rest of the counter is unused right?

Oh, wait, then maybe we're making this too complicated. All I need is /8 at 50% duty. If I have it just count 0-15 and I'm only looking at Q3, then that will be active for cycles 8-15 of 15, which is what I need. In that case I would start counting at 0, and would I still need the parallel load? Wouldn't it just roll back to 0? It seems then all I would need to do is give it the clock, enable the count, and only look at the MSB for my CLK/8 at 50%

Alright, that makes perfect sense. I didn't realize the original plan was to avoid counting from zero. And right, Q2, good catch. I could actually do it with just a regular 4-bit counter or clock divider, since /8 doesn't need the extra functions of the 74163/74161 chips, but they do seem to be the cheapest solution.

Thanks a lot for the help.

-Austin