ADAU1701 I2S Input
Hi,
I have a working ADAU1701 solution using Analog Inputs but need to add an external SPDIF with SRC @ 48k output to the design.
Setup as follows and attached jpegs:
1) ADAU1701 as Slave to external 256fs MCLK.
2) Data, BITCLK, and LRCLK connected to MP1-Input Sdata-1, MP4-Input LRCLK, MP5-Input BCLK and MCLKI
3) SCH Input Block 1,2,4 & 5 Active
4) Programable MUX Nx2-1
Note: when using Analog input and SPDIF Not Locked signal throughput is good.
Note: when SPDIF locks and all data and clks present at ADAU1701, MUX switched to I2S input 4&5, result is NO signal throughput.
What am I missing???
Are there any eval applications available with I2S functioning?
What is the 1701 expecting for BIT Clk rate 64fs?
Is I2S 24Bit input OK?
Thanks,
Daniel
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hi Daniel,
Your setup appears to be correct. The bit clock signal pin expects 64 x Fs, which is 3.072 MHz for a 48 kHz sample rate. The LR clock signal should be the sample rate, or 48 kHz. The bit depth is 24 bits, with a one bit delay from the LRCLK edge to the start of the data. That's programmable as well, using the register settings, with options of 0 BCLK delay or various right-justified modes. Can you attach a picture of the clock signals?
I mapped the 12.288MHz clock to the input of the DSP and all is good. Thanks, Dan
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