ADAU1701 BCLK jitter
I'm working on a custom design using the ADAU1701. I have some problems with the external I2S interface.
The internal ADC and DAC are working fine if no I2S is connected. I am using the 1701 in I2S master model, with BCLK out tied to BCLK in and the same for LRCLK. When I try to drive my ASRC (SRC4192) in slave mode with the I2S from the 1701, the ASRC has trouble locking to the signal, and the data is not in sync with the LRCLK.
When I look at the BCLK signal with my scope the jitter is huge! There is jitter even if everything is disconnected except for the scope probe. It's about 40 ns(p-p). It's not my MCLK, as that is very clean, and running the ASRC as I2S master generates a jitter free BCLK. What could cause this jitter on BCLK? I checked the PLL filter and it's as the datasheet specifies. I replaced the ADAU1701 IC and the problem remains.
Another very strange problem is that adding capacitive load to the BCLK signal messes up the internal DAC. Are these somehow tied together inside the 1701? Even adding something like 30 pF to the BCLK causes dropouts from the internal DAC. I suspect this is related to the first problem somehow.
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Something strange is going on with this BCLK signal. I was able to get it to work by generating my own BCLK signal that is phase adjusted to the LRCLK, and everything else being the same. Why does BCLK have so much jitter?
Hello,
This sounds characteristic of instability of the internal MCLK in the ADAU1701. There are a number of factors that could be contributing to the issue.
PVDD Supply: How clean is the PVDD supply? Is there any noise or ripple? The VCO is referenced to PVDD, so any AC component on this supply could cause the internal clock to vary in frequency, thus making it difficult for the PLL to maintain lock. That would create a jittery MCLK, and since BCLK is generated from MCLK, this would affect BCLK as well.
MCLK Source: Are you using an external MCLK source or the crystal? If you are using an external MCLK source, what is the jitter on that source? If you are using the internal oscillator and an external crystal, what type of crystal are you using? The datasheet recommends an an AT-cut (quartz) parallel resonator operating at its fundamental frequency.
Crystal Circuit: The crystal circuit includes two load capacitors that should be specified to match the capacitive characteristics of the PCB. There is an equation in the ADAU1701 datasheet that shows how the load capacitance should be calculated. On our PCBs, we use 22 pF load capacitors, but that may vary depending on the board you are using. Improper specification of load capacitance can lower the stability of the crystal circuit and increase jitter in the system.
PCB Layout: Noise coupled from other components on the board can corrupt the supply lines and cause timing issues on the SigmaDSP. A solid ground plane and standard mixed-signal PCB design techniques should be followed in order to properly deal with noise in the system. Are you following the PCB layout guidelines detailed in this best practices FAQ? https://ez.analog.com/docs/DOC-1889
Please log in to reply.