SSM2603 noise in ADC path
I am validating a SSM2603-based design and noticed an audible hissing noise in supposed-to-be silent recordings. What the FPGA-based test project does is record 2s of stereo audio on linein (96kHz, 32-bit I2S format), play it back on headphones and repeat. Here is what I managed to find out so far:
- during playback of constant digital 0, bypass and sidetone disabled, no noise
- during playback of constant digital 0, bypass enabled, no noise
- playback of past recordings, noise appears
- noise appearing in ADC output (RECDAT, BCLK, RECLRC)
- noise frequency different in left and right channels: 3.2kHz left, 800Hz right
- noise amplitude 11-bits out of 24
- noise amplitude unrelated to input amplifier gain (INVOL)
noise as seen in logic analyzer having the de-serialized 24-bit samples from the left channel plotted (INVOL = 0x07)
noise as seen in logic analyzer having the de-serialized 24-bit samples from the right channel plotted (INVOL = 0x07)
Configuration used:
0x0F = "000000000", -- Software reset
0x06 = "001110000", -- R6: Power up DAC, ADC, MIC, LINEIN
0x00 = "100010111", -- R0: Both-channel ADC mute disable, mid volume
0x02 = "101111111", -- R2: Both-channel headphone 6dB
0x04 = "000010000", -- R4: Sidetone disable and bypass disable, DAC to output, ADC input LINEIN
0x05 = "000000000", -- R5: DAC digital mute disable
0x07 = "000001110", -- R7: 32-bit word length, I2S mode, slave
0x08 = "000011100", -- R8: 96kHz ADC/DAC Sampling Rate, MCLK = 12.288MHz
--delay ~ 75ms
0x09 = "000000001", -- R9: Active
0x06 = "001100000" -- R6: Power up Out, DAC, ADC, MIC, LINEIN
Schematic attached.
I am having trouble determining the source of the noise. From the test results described above, it seems to me that the noise is introduced by the ADCs. Any ideas on possible noise sources or tests I could conduct to narrow the issue down are welcome.
Message was edited by: elodg Added schematic attachment
adc
ssm2603
Integrated/Special Purpose A/D Converters
noise
Audio CODECs
Elod:
I'm shocked that you are getting this level of performance. when powering directly from the FMC connector.
Remove FB2/FB3, and power from a lab suppy, and see if the noise goes away.
Also - noise can get into the part from DBVDD - this should have some filters on it as well. See the schematic in the datasheet - Fig 31 - the DBVDD is powered from the analog supply - not the digital one.
I would think that you would want a 5V -> 3.3V analog regulator, with good power supply rejection in the audio spectrum. I can give you some pointers if you want.
-Robin
Robin, thanks for your input.
I tried externally supplying 3.3V to AVDD and HPVDD and 2.5V to DBVDD. I cannot discern any change in the noise amplitude or frequency. Now the core supply is the only one still powered from an FMC supply pin.
I am confused by why the Digital I/O supply is tied to the analog power supply in the typical application circuit.
Recently, I also tried if using a crystal oscillator rather than an FPGA clock helps. It doesn't.
Elodg:
The pin is tied that way since that is the way we recommend it to be done. Noise on this pin will couple into the analog section.
How much noise is on this pin? Does it correlate to the noise on the outputs?
-Robin
I am seeing 20mVpp AC noise max on the power supplies, but at frequencies seemingly unrelated to the audible noise. With the 50dB PSRR of the SSM2603, this equates to ~9 bits of noise, if my calculations are correct. This might account for a quarter of the noise.
I am still not entirely convinced that the noisy supplies are the #1 culprit, but I do agree that clean supplies are needed for high quality samples.
What LDOs would you recommend, keeping in mind that the input voltage has to be VCC3V3? Also, the digital I/O interface powered from VADJ, which needs to be adjustable in the 1.8V-3.3V range and thus, DBVDD too.
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EZ Admin
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