ad1937 - asking internal PLL

song Question

Oct 5, 2011 00:00

Hello, AD Engineers.

I am testing ad1937 DAC slave mode and I have some noise issue from ad1937.

Actually I am using independent clock source for DSP and AD1937 MCLKI. I think that different clock source can cause noise, because ad1937 master mode doesn't have any noise and even when I set PLL source to DLRCLK in slave mode, the noise is gone.

Here, I have a question about using internal PLL.

When I set PLL input as DLRCLK, sometimes PLL lock is set to 1 but sometimes lock bit isn't set at all, also there is no audio out from DAC.

Is there some limitation about using internal PLL? For example, PLL input frequency should be 48kHz.

Because I tried to use 44.1kHz for LRCLK, the pll lock bit wasn't set.

Can you please explain to me how to use internal PLL?

One more question is,

Is Bit 2:1 in PLL and Clock Control 0 Register meaningful just for that PLL input is MCLKI/MCLKXI? or does that field determine pll frequency?

To help understand my clock condition, I attached block diagram.

Is it possible for having noise in slave mode?

Thanks.

Songhee.

slave-mode

Integrated/Special Purpose A/D Converters

noise

Audio CODECs

ad1937

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ADIApproved Reply

Oct 5, 2011 00:00

Hi Songhee,

You cannot use an independent master clock for both DSP and the AD1937 as the two clocks will not be synchronized, that is why you are having issues with slave mode. You can use DLRCLK as the input to the PLL as long as the input freq is > 32Khz, 48Khz should work fine. You also need to change the PLL loop filter when using the PLL with LRCLK. Please see figure 32 page 32 of the datasheet for loop filter values. Bit 2:1 should be set for 256x operation when using the DLRCLK input. You could also use one master clock for both DSP and AD1937 when running the AD1937 in slave mode.

Best Rgds,

Alan

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song Reply

Oct 5, 2011 00:00

Hello, Alan.

Thank you for your answer.

I checked the loopback filter of my board. One of capacitor value is 390pF but in Figure32, the capacitor value is 39nF.

I will try to change this cap as same as Figure32.

Thanks again.

Songhee.

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song Reply

Oct 5, 2011 00:00

Hello, Alan.

With changing loopback filter like reference circuit, the PLL lock bit is set.

Thanks alot.

Songhee.

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