dual adau1701 digital audio connection
Hi,
what is the best way to connect two sigmadsps with respect to the audio port (e.g. I2s)? They share the same master clock and audio should go in both directions.
In the manual it is described that the audio serial in can only be a slave. Would it be a good practice to make each serial out a master? This way one would have a direct connection (in hardware) which could be better from the line driver´s view?! Or would be better to make one dsp the master which have then to feed three inputs (it´s own serial inputs and in/out from the second dsp).
Are there any recommendations for termination resistors for the BCLK and data line?
Thanks in advance!
best,
rastariot
Audio Signal Processors
serial
SigmaDSP Audio Processors
audio
adau1701
Hi Alan,
thanks for your response.The BCLK is 3.072 MHz (48kHz x 64). Meanwhile I played around with different series termination resistor because I have some issue getting the serial connections to work.
In my current design DSP1 is sending data to DSP2 over an I2S connection. Both DSPs work okay, when not connected over the serial port. Everyone shows a clean and continouse output signal.
When my DSP2 gets data from DSP1 over the serial port the analog output(s) of DSP2 gets unstable. Sometimes the outputs are total zero and then the signal seems to be faded in (signal level increases over time)? Is this is a result of how sigmadsps add signals coming from ADC and from a digital input?
The digital signals (Fs, BCLK ) seem to be stable (phase and level) when observed with a probe!
Do you have a rough idea what´s going on there and what I could check?
best,
rastariot
Hi Rastariot,
You should be able to use either approach, either connect one master serial output to the three other serial ports or use the master serial output of both ADAU1701 and connect them to the serial input of the other 1701. I think having one master will be fine assuming the trace lengths between the two 1701's is short, what is your bclk rate? I would put some source series resistors on the BCLK and data lines that you can adjust to reduce ringing.
Best Rgds,
Alan
Can you check that the I2S settings match between the two DSPs (LRCLK polarity, BCLK data edge, data clk delay is 1 for i2s)? Can you describe the signal flow in more detail? Are you routing through the ADC/DSP or DAC?
Hi Alan,
yes I know, the explanation was quite short!
In my setup each dsp gets one analogue audio channel and transfers this channel via I2S to the other dsp, so that each DSP has two audio input channel that are further processed. The processed channels are sent to the DAC outputs on each DSP. So that I have in total two channels in, and four channels out!
As far as I can see my I2S config looks okay: MSB is delayed by one, LRCLK is set that left channel is present at low phase. Some settings can only be made be the master (serial out). BCLK is set to clock data out on the falling edge, and for the serial in BCLK data change on falling edge too.
Can you explain to me how sigmadsp merge the signals coming from the ADC and the digital serial in? What happens in case of frame sync loss? Is there a way to detect this from withing the DSP (e.g. register to read)?
best
rastariot
Hi Rastariot,
No, there is no way to tell in the DSP if you lose frame sync. Can you verify the I2S output by passing the data thru the DSP without processing directly to the DAC? It would be nice to try and separate whether it is a problem with the I2S or DSP processing, maybe you've already done this?
Best Rgds,
Alan
Hi Alan,
sorry for the delay in response. After a while I´ve found the mistake. It´s was a hard to find solder issue. Meanwhile all work as it should.
Thanks for helping anyway!
best,
rastariot
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