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Fundamental Questions: ADCs, DACs, I2S

SigmaDSP & SigmaStudio rsbonini Aug 4, 2011 00:00 5 replies Original on forum ↗
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rsbonini Question
Aug 4, 2011 00:00

I have a question which google (despite my trying) has not been able to answer. I hope someone here with more knowledge than I would be gracious enough as to correct my understanding on the following point:

I2S data is converted and output by a DAC relative to that specific device's own 0dBFS level and as nothing to do with the voltage the signal was originally sampled at.

example: If an ADC (0dBFS = 2.5Vpp) samples a 1Vpp signal and outputs this signal via I2S to a DAC (0dBFS = 5Vpp), the DAC would output an analog signal at 2Vpp.

Is this correct?

ADIApproved Reply
Aug 4, 2011 00:00

Yes, that's right.

The math is: (1 / 2.5) * 5 = 2.

rsbonini Reply
Aug 4, 2011 00:00

Thanks for the confirmation, knowing that for sure helped me isolate a rather nagging problem pretty quickly. I also have a question about the gain structure within the ADAU1761's dsp core. In the device datasheet,

Page 45 states:

"The input and output word lengths of the DSP core are 24 bits. Four extra headroom bits are used in the processor to allow internal gains of up to 24 dB without clipping."

Page 46 states:

"The serial port accepts up to 24 bits on the input and is sign-extended to the full 28 bits of the DSP core. This allows internal gains of up to 24 dB without internal clipping."

My question is about how this 24dB of gain is or can be preserved when being sent to an DAC.

Suppose a signal is input to the ADCs which is approximately 0.250Vpp or about -15dB below the 0dBFS (2.83Vpp) of the ADCs. After 24dB of gain has been applied to this signal, we would have a signal which is approximately +9dB in the digital domain.

According to the data sheet above there should be no clipping of this signal within the DSP core: is this true?

Should this +9dB signal be sent to an external device via I2S, wouldn't the I2S data be corrupted as the maximum 'amplitude' allowed in the digital stream is 0dB?

I am unable to test this with the equipment presently available. Any insights, or direction to detailed references on this topic and on digital gain structure in general would be greatly appreciated.

ADIApproved Reply
Aug 4, 2011 00:00

Note that there is no automatic application of 24 dB of gain in the DSP. The datasheet is just trying to show you that you can optionally apply gain that would take the signal above the clipping level inside the DSP.

Let me explain a different way...

Basically, the analog input goes through the ADC and it is mapped to a number between -1 and +1 in the digital world. So, for example, an analog sine tone that had the full-scale amplitude of the ADC would appear in the digital domain as a signal fluctuating between -1 and +1. If you had an analog input signal that was greater than the full-scale range of the ADC, it would clip and saturate at +1 or -1.

So, imagine our analog input sine wave was exactly at the full scale amplitude of the ADC. We then give you 4 extra bits of headroom in the DSP. The sine tone still remains between -1 and 1 at the output of the ADC, but now, if you were to apply some gain to it in the DSP core, you could technically increase the amplitude of the signal above -1 and 1 without clipping. Because there are 4 bits, this means your signal range extends to -16 to +16.

However, when you output from the DSP core to either the serial ports or the DAC, the signal will clip or saturate at +1 and -1 again. This means that if you were doing any processing in the core that applied positive gain to the signal, you must then attenuate the signal before it is output from the DSP core.

Take a look at the diagram.

The ADC or serial input data is 24 bits of audio (represented by As).

Inside the DSP core, you can additionally use the 4 headroom bits (represented by Hs), for a total of 28 bits.

But, at the DAC or serial output, those 4 headroom bits are chopped off as the signal is saturated back to 24 bits. You must bring the signal back down below 0 dBFS before outputting from the DSP core or else you will have severe distortion due to this saturation.

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ADIApproved Reply
Aug 4, 2011 00:00

To put it another way...

The headroom bits are there as "insurance" in case your signal flow has filtering, etc., that might cause some gain to be applied to the signal. Typically, a signal flow will have a compressor or limiter at the output for the purposes of guaranteeing that the signal will not clip on the output.

This feature is very handy because on any other DSP with fixed precision, designers typically have to scale down the signal at the beginning of the signal flow and then scale it back up again at the end, to avoid clipping within the DSP itself. That method increases the system's noise floor. SigmaDSP's headroom bits allow you to avoid that problem.

EZAdministrator Reply
Aug 2, 2018 00:00

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

Thank you,
EZ Admin