ΣSigmaStudio Ask AI Русский Log in

Clock jitter in ADAU1701

SigmaDSP & SigmaStudio seeker Jun 28, 2011 00:00 4 replies Original on forum ↗
Subscribe
seeker Question
Jun 28, 2011 00:00

Hi,

I'm trying to understand if the performance of the ADUA1701 can be improved by using better clocks.

Is it possible that the overall audio performance of the ADAU1701 can be improved by supplying an external high performance clock with low jitter instead of using the internal oscillator with a std X-tal?

Further on, there is a PLL that generates the internal clock for the DSP. Does the clock for the ADC and DAC come from that PLL or is it from the master clock (12.288 MHz) which, most likely, has lower jitter? If possible, please describe the clocking scheme in the 1701 device.

Regards,

Mats

Audio Signal Processors

SigmaDSP Audio Processors

adau1701

seeker Reply
Jul 5, 2011 00:00

All,

I can see that about 100 people have read my question but unfortunately no response so far . I hoped that someone from Analog Devices had experience from evaluation jitter susceptibility on different types of ADC and DACs. By replying to my own question I hope to trigger a response from anyone who have experience from clock jitter on overall audio performance.

Regards,

Mats

ADIApproved Reply
Jul 7, 2011 00:00

Sorry for the delayed response. I've been going full steam on a very urgent PCB design that I just finished up yesterday, and while that project was underway I unfortunately didn't have much time to spend on forum and support issues.

I'm not sure if I can answer this question well enough on my own, so I'm going to recruit some help from some IC designers who are more familiar with the effects of jitter on the audio performance.

I know that the harmonic distortion will typically increase as jitter increases because variable spacing of the samples tends to distort the shape of the signal.

The difference between using the crystal circuit and an external low-jitter MCLK source appears to be minimal, at least from my tests. The THD+N does not vary significantly when I try different clock sources on the evaluation board.

The PLL cleans up jitter from the input clock to some degree. The ADAU1701 serial ports also have de-jitter circuitry that delay the latching of data so that no samples are dropped or duplicated.

I'll check with a few other people to see if they can add additional comments to this thread.

seeker Reply
Jul 8, 2011 00:00

Thanks BrettG for coming back. I think I'm currently on about the same level of knowledge on clock jitter as you describe in your response.

I often get feedback from other users of DAC chips that the audio sounds considerable better with high stability oscillators with low clock jitter. I haven't really seen a close correlation between measured DAC performance and audible results. As an engineer I beleive in measured results but I also trust my ears.

I've used the ADAU1701 with good results but if the performance can be increased further with a better oscillator or selection of PLL configuration or external components, it's maybe an easy win.

It would be fantastic if you could provide more insight on this topic when you have checked with other people.

/Mats

EZAdministrator Reply
Aug 2, 2018 00:00

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

Thank you,
EZ Admin