ADAU1701 I2S, PCM
Have several questions regarding output of I2S on an ADAU1701. To be clear, the board is one of our own, however, the schematic is as shown on Pg 51 of the datasheet (I2C control) without any of the DAC wiring and PLL mode 0 and 1 tied high.
1) On the inputs, there is a selection as to what type of serial data (I2S, LJ etc), however, on the output section of the serial data, there is no similar box. If I want to input Right Justified PCM and output to I2S is there any way I can do this?
2) I've been trying to use the ADAU1701 as a master clock driver, however, the external chips I am using behave poorly at the clock signals that I am generating. The clock transitions are clean, however the lowest frequency I can obtain is about 767kHz (12.28MHz/16) is this correct?
3) So to circumvent the problem, I change the external chip I am using to master mode, however, the ADAU1701 doesn't seem to recognise the external clock until I wire the output pins MP11 (output b_clk) to MP5 (input bclk) and MP10 (output lr_clk) to MP4 (input_lrclk)? Is this correct? As I pass the output signal back to the chip, it has trouble recognising it, thus I am uncertain whether or not the format is incorrect (q 1 above) or if the clock is being processed incorrectly.
Thanks in advance for anybody's help
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
1) On the output side, format is adjusted using the MSB Position control. Left-Justified is delay-by-0, I2S is delay-by-1, 24-bit right-justified is delay-by-8, etc...
2) Exactly what signals are your driving to external ICs? Just LRCLK and BCLK, or also MCLK? LRCLK and BCLK can be driven directly from the pins, but MCLK needs to be buffered - it cannot be taken directly from the OSCO pin.
3) If the ADAU1701 is the clock master, then you need to put the output port in master mode and connect the output-LRCLK and output-BCLK to the input-LRCLK and input-BCLK pins.
I am attending a technical conference this week so my additional reponses to this thread may be delayed.
Thank you for your prompt and thorough answer! A few more questions though
1) That answers lots of questions thank you
2) Just LCLK and BCLK are being driven by the chip, the external chip I am using doesn't appear to want to take a clock above 383kHz. Is the lowest I can generate with the ADAU1701 double that?
3) What if the ADAU1701 is the slave? Do I also need to connect output-LRCLK and output-BCLK to the input-LRCLK and input-BCLK pins?
2) Standard BCLK frequency for the ADAU1701 is 48000 * 64 = 3.072 MHz for a 48 kHz sample rate and 44100 * 64 = 2.8224 MHz for a 44.1 kHz sample rate. For 96 kHz the BCLK is 6.144 MHz and for 192 kHz the BCLK is 12.288 MHz. So, you can see that even the slowest rate is about 10x greater than the 383 kHz you mention. Where does that number come from? Are you interfacing to a standard I2S audio port?
3) If the ADAU1701 is a slave, you have to connect the external BCLK and LRCLK signals to both the input and output sides, assuming you're using both the input and output ports.
okay, the 384khz comes from 8000 hz * 48
i have the adau chip talking to a bluetooth audio chip paired to a headset running a hands-free protocol stack that requires 8kHz mono communication. i think that means the LR clk needs to be 8kHz whatever else i do.
is there a way to do this?
theoretically, if i have bclk to be (192 x 2) x 8kHz = 3.072 Mhz, is there a setting to keep LR clk at 8kHz? that means having 192 bits per channel. we'd only use 1 bit for delay, and the following 16 bit to encode data. the rest would be padded with zeroes. but i can't seem to find a way in sigma studios to set this up.
thanks for you help again.
Unfortunately, the ADAU1701 can only run at sample rates like 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz. Please check the datasheet, page 40.
SR[1:0] Sample Rate. These bits set the number of DSP instructions for every sample and the sample rate at which the ADAU1701 operates. At the default setting of 1×, there are 1024 instructions per audio sample. This setting should be used with sample rates such as 48 kHz and 44.1 kHz.
At the 2× setting, the number of instructions per frame is halved to 512 and the ADCs and DACs nominally run at a 96 kHz sample rate.
At the 4× setting, there are 256 instructions per cycle and the converters run at a 192 kHz sample rate.
You can also see this on the MCLK period specification on page 8:
tMIN = 73 ns, tMAX = 488 ns, (256 × fS mode)
This shows that the minimum rate the chip can run at is a little more than 32 kHz.
If you want to run at 8 kHz, try the ADAU1761 or ADAU1781, which can run their converters, DSP, and serial ports at any rate between 8 kHz and 96 kHz.
Hi
hope you are doing great
"This shows that the minimum rate the chip can run at is a little more than 32 kHz."
From your last reply I have one question, can you please explain , how it is 32 Khz ? and what does minimum rates means ?
Thanks in advance.
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