Sigma DSP integer/fraction

Since there are no bit-wise operators in SigmaStudio (yet), this is a bit tricky.

I would suggest the following approach:

To get the integer part, you need to bit-shift to the right 23 places and then back to the left 23 places. This will truncate the lower 23 bits. Unfortunately that requires a lot of processing to do.

If you read back in 28.0 format, it looks like this:

You're basically bit shifting to the right 23 bits by multiplying the input by 1 LSB. Note that the input is 12.34567 and the output is 12.

If you need to read back in 5.23 format, it gets more complicated:

The multiplies are essentially bit shifting back to the left.

Unfortunately you can't use the same method in reverse to get the fractional part, because upper bits do not truncate, they saturate. Until we get a bit shift algorithm implemented, I'm not sure how you could do that. You could probably use some logic cells or RMS table to subtract integers from the signal based on certain constraints until you get down to zero. That won't be too hard to implement, but will take a fair bit of resources.

This is fine for 5.23 values < 16 (15 buffer samples). However, how would you apply this to something in the 500 sample range?

I don't see a solution. It seems that there would be insufficient resolution for the fractional part.

Good news! We are releasing a new "Bitwise Logic" cell that will allow you to mask the number and output the result. Here's an example of how it will work:

Sorry if it's a bit hard to read. In each example we compare two numbers. One comparison uses the standard logic cell, which basically just compares (is zero?) and (is non-zero?). The second comparison shows the bitwise logic cell, which does a true comparison of each bit in the word.

So if I did 0101 AND 0011 I would get an output of 0001. If I did 0101 OR 0011 I would get 0111. Get it?

Using this cell, you could AND a number with 1111100000000000000000000000 to get the integer part, and AND the number with 0000011111111111111111111111 to get the fractional part.

The new cell should be included in the next SigmaStudio beta release.

I'm guessing this will substantially reduce the processing time (most likely a single instruction?) which is good news. When will this be available?

BTW - I was able to eliminate the noise with the fractional delay implementation.

For larger delays, say 1024 samples, could 11/17 format be used to provide the integer/fractional part of the delay?

We try to do beta builds about twice per month, so hopefully it will be available in the beta soon. I'm not sure of the exact release schedule.

You can condition the signals to fit any number format you require within the DSP. Just be sure to scale the signals accordingly for when you get to our index cells, since they have a fixed format (28.0).

I was able to scale this up for a delay of 1900 samples with appropriate bit shifing. Do you have an ETA on when the new SigmaStudio release will be?

Will the afore-mentioned block be included? How many CPU cycles will this consume? Also, can you guys provide a VCdelay block that utilizes the fractional part for smoother delays (i.e. fractional delays)?

These bitwise logic cells are available in the 3.4 build, which is on the website now.

Brett,

I used these cells to extract the integer and fractional parts.

However, I am having an issue that is driving me nuts. The fractional delay works as expected when going from 0-->1900 samples.

Upon going the other direction, an anomoly is produced at exactly 10 samples from where the integer changes. Otherwise the waveform is as expected.

It makes no difference if I change the input frequency of the audio or the sample rate. I am at a loss for why this is happening.

Please advise.

Bob, I'm having a lot of trouble visualizing this in my mind. Could you include examples, such as a schematic or signal captures?

Brett,

I'll send the design to support.

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Thank you,
EZ Admin