About PLL Problem?
I built an own circuit with this ADAU1701 DSP and with an stm32f103 microcontroller.
In the datasheet of the DSP (page 15.) is a description about the sequence of the initialization.
1. Apply power to ADAU1701
2. Wait for PLL to lock
3. Load Sigma DSP program and parameters
4. Set up registers
5. Turn off the default muting, clear data registers and initialize DAC setup register
How do I know PLL is locked?
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
The specifications section of the ADAU1701 lists the PLL's maximum lock time as 20 ms (for an input MCLK of 12.288 MHz).
If you scale the input MCLK up or down, the PLL lock time will scale linearly with it. A 10% lower MCLK frequency, for example, will require about 10% longer for the PLL to lock.
OK, I see
Thanks a lot!
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