Low group delay ADC and SigmaDSP?
For my application involving a control loop, I need an ADC with low group delay or conversion time (<10µs) to ensure stability. Unless I missed something, there is no such ADC on any of the SigmaDSP and this is not compatible with sigma-delta converters.
Is it possible to easily connect a 16 bit 48kS/s SAR ADC to a SigmaDSP (ADUA1701, for example)? The SAR ADC product range from Analog being quite large, I've identified the AD7684 with differential input. Would that chip be suitable and how to use it with the ADUA1701?
Thanks for your help.
Audio Signal Processors
Single Channel A/D Converters
adc
ad7684
SigmaDSP Audio Processors
Precision A/D Converters
SigmaDSP
adau1701
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All of the SigmaDSPs have a standard audio serial port for transferring digital data in and out. These serial ports support I2S and other standard audio formats with a frame clock, bit clock, and data. The supported formats are fully-described in any of the SigmaDSP datasheets. The SAR ADC products probably do not have an I2S port. I'm not familiar with the serial formats that these ADCs might support, so I'm not sure if they can be put into a mode where they would work with the SigmaDSP's serial ports.
Yes, the SigmaDSPs support 2-channel I2S, Left-Justified and Right-Justified modes as well as 8-channel TDM. The single channel AD768x ADCs support classical SPI interface timing that is, if I'm correct, a right-justified single channel data transfer with chip-select, similar to the right channel on the Right-Justified audio mode. The problem lies in the timing for the left channel (into the SigmaDSP) or the high CS state (out of the ADC). It may work if the ADC clock (DCLOCK) is well chosen to have a consistent timing (24 times the chosen sample rate, say 1.152MHz) so that the CS high state is equal in duration as the low state, with the drawback to give a higher conversion time (around 14µs).
Would that work? No clue. Any thoughts welcome.
After more thoughts and further analysis of the SPI and serial digital audio timing schemes, I've ended up with the conclusion that the bridge between the AD768x ADC and a SigmaDSP should be performed by a (small) CPLD or use an obsolete ADC such as the Burr Brown PCM1750 with DF1750 (not really sensible).
Ce message a été modifié par: LHR, further analysis
The connection here would be a bit tricky because the SAR ADCs and SigmaDSPs have different interfaces. The SPI interface data format on the AD7684 resembles the I2S standard, but there are definitely some differences. Right now I'm contacting some support engineers from the SAR product line to see if they've ever had experience with a connection like this.
I have a feeling this will not work, but for the moment I will do some research and post back here when I have a more definite answer.
I managed to get some support on this issue. Sorry for the delay.
It turns out that the two interfaces will not match. They are quite similar, but the difference in MSB position, the duty cycle of the clock, and the number of clock cycles per sample that the AD7684 outputs will not match what the ADAU1701 expects.
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