Read Requests and DSP_ENABLE

To do a read over I2C, there must first be a read request to set up the transaction. This process is illustrated in Figure 50 of the ADAU1761 datasheet. These appear as two different entries in the Capture Window.

DSP_ENABLE does not clear parameter and data RAM by setting it low.

Furthermore, when the capture data is copied to the export window, the original read request is eliminated and replaced by a block read of the PLL. The original block read of the PLL is removed. Why? Is there any other data removed, modified, re-sequenced, etc. from the orignal capture window when data is copied to the export window that we should know about?

Additionally, when the data is exported, the Mode 0_TxBuffer.dat file has an incomplete data entry for the PLL register - see line 60.

This happens for both SigmaStudio 3.1 and 3.2.

Does this apply to SPI as well? I am not using I2C.

Figure 56 in the datasheet shows an example read using SPI. You need to write the address which is to be read to the ADAU1761, which will be followed by the data being output on the COUT pin. Up to that point, COUT will be tri-stated.

Ahh, I see what you mean, now. The confusion is the way that the capture window is displaying the readback data. The placement of the read data in the capture window is not where you would see it if you were looking at the signals with a scope or signal analyzer. The data read will happen just as it's shown in the timing diagrams in the datasheet. I think that what you're seeing in the capture window is just a result of displaying the data readback being delayed as it's processed on the PC. Electrically (the signals, on the board), the read back happens immediately following the read request. There are not additional register writes in between the read request and the data being output from the IC.

Here is where the confusion lies....

The capture window shows first a READ REQUEST, then a READ several transactions later?!.

How can you have a read request transaction followed by subsequent writes to the DSP_RUN, SAMPLE_RATE, DEJITTER, and DEJITTER registers and THEN have the I2C READ phase (for the previous READ REQUESTed address)? Any subsequent write after the READ REQUEST will change the sub_address. I2C read protocol for the chip is START ---> (chip_adr, RW=0) ---> sub_address ---> RESTART (chip_adr, RW=1) ---> data(n) ---> STOP.

Up until now, I have assumed that the capture window shows COMPLETE transactions from START to STOP.

So, to me, I see 2 separate reads (at different times) of the PLL register. From what you're saying, the REQUEST and its READ are for only 1 transaction per the I2C spec, correct?

If this is the case, I can now understand why the READ part of the transaction is dropped from the .xml file (exported data)

I'm guessing that the REQUEST part was issued first and the data was EVALUATED at some later time per the capture window time stamp?

Obviously, for SPI reads, you don't need a "request" phase. What was unclear was whether I needed 1 or 2 reads of SPI due to the confusion over the number of I2C transactions needed to read the PLL register.

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Thank you,
EZ Admin