SigmaStudio and cosine/sine
Hello,
I just got an ADAU1701 Mini Evaluation Board. I am using SigmaStudio 3.1.
For my programm, working at 192kHz item sample rate, I need to generate both a cosine and a sine at 40kHz.
I have two main problems :
First, there is no cosine generation function. I somehow managed to create a cosine by using sin(2*a)=2*sin(a)*cos(a), but it uses up 2 sine, and there's a wrong point when sin(x)=0 (cos(x) should be 1, it is 0).
Another problem, concerning the sine functiun, is that, even if the sample rate is set over 48kHZ, it will work at 48kHz maximum. So at 192kHz, the frequency is divided by 4...
Any suggestions?
On another note, is there a way to use the output of a function (the sine generation function for example) two times (ie. linking it to two other functiuns) ?
Thanks for your help,
Regards,
Matthias.
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
The sine tone generators in SigmaStudio support frequencies up to fs/2. Check this FAQ to ensure that you're properly setting up your hardware for higher sampling rates: https://ez.analog.com/docs/DOC-1431
A cosine is simply a sine shifted by 90 degrees. You can shift the output of your sine wave with a delay block, which has 1-sample resolution, but this may not be good enough for your application. This resolution cannot create a 2nd signal that is exactly 90 degrees out of phase with the first. With fs=192 kHz, your sampling period is about 5.21 us. A quarter wave length (90 degrees, or pi/2) of a 40 kHz signal has a period of 6.25 us. So, you can see that method will give either a phase shift that's less than 90 degrees (1 sample) or more than 90 degrees (2 samples). Of course, this simple delay solution will work better for signals at lower frequencies.
You can use a t-connection cell (in the Schematic Design library in the toolbox) to send the output of a single block to the inputs of multiple blocks.
Could the system simply be run at 160khz which would cause a sample period
to be 6.25us ?
The PLL has an operating range of nominal +/- 20%. Nominal in the case of the ADAU1701 means 12.288 MHz, so the range is 9.83 MHz to 14.74 MHz, but since the core cannot run faster than 49.152 MHz, the upper bound on the PLL input should be 12.288 MHz.
Running in quad sample rate mode (nominally 192 kHz) at a 160 kHz sample rate means the PLL is running at 83.3% of nominal rate, which is a 10.24 MHz input MCLK. This is technically within the bounds of the device, but the performance of the analog components may differ from what is shown in the datasheet. SigmaStudio does not support a 160 kHz sample rate mode, so you'll have to manually calculate all frequency-dependent coefficients yourself. For example, even though you're trying to generate a 40 kHz sine wave, you'd have to input 33.333 kHz into the corresponding control in SigmaStudio to get the appropriate frequency scaling.
Thanks a lot for your help.
Configuring the hardware like in this FAQ : https://ez.analog.com/docs/DOC-1431 and using a one sample delay works just fine.
However, I have a last question : I changed the hardware configuration in order to run at 192kHz, reducing the program length. Now, by looking into the datasheets of the ADAU1701 and the evalboard, I noticed that the evalboard is using a 12.288MHz oscillator with the PLL_Mode0&1pins in configuration 01, i.e. 256xfs.
Now if I use, in my futur design, the ADAU1701 with the same oscillator but with PLL_mode in configuration 00, i.e. 64xfs, the DSP should be working at 192kHZ, allowing me to use full length programs.
Would that work?
Unfortunately at a 192 kHz sample rate, you will always be limited to 1/4th of the program instructions, regardless of the PLL settings. The concept is a little complex, but I think the discussion in this thread will probably help to make it understandable:
Ok, thanks a lot.
Please look at this article for a method for generating a sine and cosine with the same frequency using multiply, add, and delay cells. I will try to implement this in SigmaStudio when I have free time.
http://www.earlevel.com/main/2003/03/02/the-digital-state-variable-filter/
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