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24kHz sampling on ADAU1442 - achieving the highest core clock

SigmaDSP & SigmaStudio IanH Jul 1, 2010 00:00 2 replies Original on forum ↗
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IanH Question
Jul 1, 2010 00:00

My application has all sampling at 24kS/s and the ADAU1442 is the clock master.

What is the best way to set up the ADAU1442 crystal, clocking and PLL to maximise the processing cycles available for my application with 24kHz sampling?

At 48kHz normal rate, 3584 instructions can be achieved per sampling instance.

Can 7168 instructions be achieved at this 24kHz "half-rate" sampling?

I also want a synchronised clock out to feed to my FPGA so that other digital audio processing can be achieved. This should be the highest rate possible. What frequency can be achieved and how would I set it up?

Thanks in advance.

Audio Signal Processors

adau1442

SigmaDSP Audio Processors

ADIApproved Reply
Jul 6, 2010 00:00

The ADAU1442 can execute a maximum of 3584 instructions/cycle. Lowering your sampling rate below 48 kHz will not gain you more processing cycles.

You can use the CLKOUT pin to output a buffered master clock to other ICs in your system. Table 9 on page 23 of the datasheet shows the different options for setting up this pin.

EZAdministrator Reply
Aug 2, 2018 00:00

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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EZ Admin