Large delays with ADAU1701/1702

One of the tradeoffs of the low cost of the SigmaDSP processors is the lack of an external memory interface. This feature was left out because the majority of target applications for the ADAU1701 require delay memory only for speaker alignment, which is usually on the order of a few milliseconds.

For a long, uniform delay, I see only one option, really.

Assuming the system is analog I/O, you could use the serial output ports to pump the data out in I2S format to an external IC (perhaps a microcontroller with a RAM interface -or- a dedicated I2S audio buffer chip), then bring the data back in through the ADAU1701's serial input ports.

Another possibility is the use of an FPGA w/memory, since you would need to design the I2S interface anyway. Factors to consider would be the amount of memory needed for your delay requirement which also impacts cost. Also, a smaller FPGA for the I2S interface coupled to an SDRAM would be an alternative.

Similar Thread: https://ez.analog.com/thread/4159

I have a question related to this:

When in a design with ADAU1701 I try to add a delay block, I can adjust the max and real values to, say, 3000 samples. I don't think this is even possible, but the system allows me to compile (SigmaStudio 3.2) and the generated compiler_output.txt shows only very marginal increase in the resources used. Is it that the delay isn't really been applied, or that the software doesn't inform about the resources used? I would have expected to see a drastic increase in the data RAM resources used.

This seems to be a bug in how SigmaStudio's compiler is handling the memory allocation with the delay cells. I've let our software team know about this, so it should be fixed in a future revision of the tool. In the meantime, you should just limit the total of all of your max settings on the delay cells to less than the total data memory available on the SigmaDSP you're using. In your case with the ADAU1701, this maximum setting is 2k samples of memory. If you do not exceed this maximum setting, your compiler output should give you a proper report of resources used.

Please keep in mind that delay blocks are not the only cells that use the data memory. Filter will each use some data memory locations and a wire between cells will use a data memory location as the data is moved from one processing block to the next. So, in your design, you won't be able to apply the full 2k samples exclusively to the delay cell, but the majority of the data memory can usually be used for this purpose.