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Problems with ADAU1701 in TDM Mode

SigmaDSP & SigmaStudio Robin Mar 17, 2010 00:00 4 replies Original on forum ↗
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Robin Question
Mar 17, 2010 00:00

Hi there,

I am using in a new project the ADAU1701 together with an external 6/8ch CODEC in TDM mode..
Everything's seems to work fine, but I cannot get any signal on MP6 (TDM 8ch out). The output BCLK is fine (set to 12.288 MHz) and output LRCLK (48 kHz) is present as well, but no data signal.

Here are the conditions:

- Sampling Rate: 48 kHz
- SCKI: 24.576 MHz (= 512x fs) from external oscillator (PLL0 and PLL1 set to "high")
- Serial Output set to "Master" and "TDM enable" activated. MP's set properly for TDM mode-
- Signal input is in "TDM" mode as well. In this caes the ADC of the CODEC is "master", the DAC's are slave.

Is there any required setting in the registry that I missed? Or can the ADAU1701 not handle "TDM" mode with
SCKI = 512 x fs (24.576MHz)?

Any help is highly aprreciated.

Regards,

Robin

Audio Signal Processors

SigmaDSP Audio Processors

adau1701

ADIApproved Reply
Mar 18, 2010 00:00

Robin,

The ADAU1701's serial port does not support a 24.576 MHz BCLK. The INPUT_BCLK pulse width hi+low in the datasheet's spec table is 80 ns, which is a maximum frequency of 12.5 MHz.

Since you are already generating a 12.288 MHz BCLK from the output port in master mode, you should just connect the master serial output clocks to the serial input clocks and the ADAU1701 should work in TDM mode.

Robin Reply
Mar 19, 2010 00:00

Thanks for your quick reply, but Input BCLK coming from CODEC is 12.288 MHz only and therefore identical with output BCLK. Only the system clock is 24.576 MHz. Is it nevertheless necessary to connect input BCLK and output CLK pins?

Regards,

Robin

ADIApproved Reply
Mar 19, 2010 00:00

If the BCLK coming from your codec is 12.288 MHz, then you should use that as the BCLK for all of the serial ports. This will make it so that you only have one clock source in your design, so all of the serial ports will be synchronous. You can use the BCLK output from your codec (master mode) as an input to the ADAU1701's INPUT_BCLK and OUTPUT_BCLK pins, both operating in slave mode.

EZAdministrator Reply
Aug 2, 2018 00:00

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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EZ Admin