AD1445 ASRC Lock status bits
Thread Summary
The user reported issues with the ASRC lock status bits on the AD1445, which are always 0 despite proper data synchronization. The support engineer confirmed that the datasheet is incorrect: the lock bits indicate output clock lock status, are active-low, and are sticky, rendering them unreliable for monitoring input clock lock. The watchdog register issue is under investigation.AI Generated Content
It seems those lock status bits on AD1445 (reg 0xE101, 0xE141) are not updated or not reflecting the realtime lock status. I'm using both ASRCs on AD1445 to synchronize two slightly out-of-phase clocks (both are 48Khz), one for input data and the other for output data. I can get data in and out properly, but the ASRC lock status bits are always stuck in 0. According to the datasheet, if the lock status is 0, the ASRC will automatically mute itself, aparently it didn't. Are these lock status bits reliable? or should I not worry about it even if they are 0s?
Speaking of registers, I remember one other issue, which is the Watchdog Value 2, I couldn't seem to be able to update the upper 8bits of that register. The datasheet says it's 16 LSBs of the watchdog maximum count. It's more like it was 16 MSBs and only 24 bits of watchog count were allowed.
Hello Rong Shen,
I'm sorry for the late response, but I've been investigating this in detail with the designers. There does appear to be a mismatch between the functionality described in the datasheet and the observed functionality of the device. It's possible that there was a mistake in information transfer when the datasheet was created. I'll reply to this thread again when I have more information.
Hello Rong Shen,
Thanks again for bringing this to our attention. I think I've gotten to the bottom of the ASRC lock bit issue. The datasheet's description of the lock status bits is indeed incorrect. Here is the correct description:
The ASRC lock bits describe the status of the output side (not the input side) of the ASRCs. Basically, it shows if they have been able to lock to an output clock, not to an input clock. They are active-low, meaning that they will be set to "0" once lock has been achieved. They are also "sticky," which means that they will not change back to "1" even if the output side clock is removed. They will only be set back to "1" upon reset and reprogramming of the device.
This functionality renders these lock bits fairly useless in an actual system. The ASRC mute ramps will never activate because the "sticky" lock bit will never reset to "1." The only practical use would be to monitor the status of a slave clock on a serial output port (the lock bit will be set to "0" once the clock is detected).
I intend to update the datasheet as soon as possible to describe this anomaly.
I'm investigating the watchdog register now.
This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.
Thank you,
EZ Admin
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