Is it possible to change the frequency of MCLK while a SigmaDSP is in operation?

Assuming the PLL is in use... When a device is powered-on and the reset pin is released, there is an initialization period during which the PLL locks to the incoming MCLK signal. Once lock is achieved and initialization is complete, the MCLK cannot be changed or interrupted during operation of the device. If the MCLK changes too rapidly, the PLL will lose lock. It will not be able to lock again to an incoming MCLK of a different frequency until the device is reset. Therefore, the reset line should be pulled low prior to changing the MCLK frequency, then pulled high again after the new MCLK is established. After initialization, the register and RAM contents will need to be downloaded again since a reset will clear the memories. Also, all parameters for frequency-dependent algorithms like filters will need to be re-calculated.

On some SigmaDSPs, it is possible to change the core frame rate (sample rate of the core) by setting a register that allows for double-rate or quad-rate processing. This would allow a 48 kHz system, for example, to operate at 96 kHz or 192 kHz without changing the incoming MCLK frequency. In this case, new parameters for frequency-dependent algorithms like filters will need to be re-calculated. Also, the program length must match the allowable maximum instruction count for that sample rate.

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