audio routing question

I'm not sure this is the right place to post this or not, but I found a documentation error in ADAU1445/ADAU1446 datasheet (rev. A). In Serial Output Port modes Registers (Page 41), Clock domain master/slave select bits for slave selecting are wrong, although the SigmaStudio seems to be using the correct ones (from the capture output). It took me several hours to find out, I wonder people at ADI may want to update the datasheet sheet so it doesn't cause troubles to other folks. Thanks.

Hello Rong Shen,

This is a very uncommon situation. How often will the TDM channel order be changing?

Your logic makes sense, but unfortunately we have not implemented bit-shifting functions in SigmaDSP, largely due to the fact that they simply do not exist in the core architecture. You could, however, use multiplication by powers of 2 to shift to the left and multiplication by powers of 1/2 to shift to the right, and then use the library's basic logic functions (and, or, nand, etc...) to read and remove the encoded channel information from the data stream. You could also use the multipurpose pins as inputs to a decoder that would control a series of multiplexers in the DSP in order to change the routing of the input channels.

Unfortunately, it doesn't look like this will be an easy solution, but I think the tools are there to make it possible.

Thanks very much for the report about the datasheet error. I have confirmed this typo.

SigmaStudio appears to be correct, so please use it as a reference.

The proper bit description for the serial output ports should be as follows:

[13:10] Clock domain master/slave select

0000 = slave to Clock Domain 9 (Port 0)
0001 = slave to Clock Domain 10 (Port 1)
0010 = slave to Clock Domain 11 (Port 2)
0011 = slave to Clock Domain 3 (Port 3)
0100 = slave to Clock Domain 4 (Port 4)
0101 = slave to Clock Domain 5 (Port 5)
0110 = slave to Clock Domain 6 (Port 6)
0111 = slave to Clock Domain 7 (Port 7)
1000 = slave to Clock Domain 8 (Port 8)
1001 = master, clock is fS,NORMAL
1010 = master, clock is fS,DUAL
1011 = master, clock is fS,QUAD

Note that the Port # in parentheses indicates which serial output port is set to which default setting.

The serial input ports' corresponding bit descriptions should be as follows:

[13:10] Clock domain master/slave select

0000 = slave to Clock Domain 0 (Port 0)
0001 = slave to Clock Domain 1 (Port 1)
0010 = slave to Clock Domain 2 (Port 2)
0011 = slave to Clock Domain 3 (Port 3)
0100 = slave to Clock Domain 4 (Port 4)
0101 = slave to Clock Domain 5 (Port 5)
0110 = slave to Clock Domain 6 (Port 6)
0111 = slave to Clock Domain 7 (Port 7)
1000 = slave to Clock Domain 8 (Port 8)

1001 = master, clock is fS,NORMAL
1010 = master, clock is fS,DUAL
1011 = master, clock is fS,QUAD

Revision B of this datasheet has already completed the publication process and can no longer be edited, so this update will be made in revision C.

Nornally this slot changing wouldn't happen until cpu runs into underrun conditions, which is rare with a proper design, but I did see it happened. I was trying to bounce some ideas around and see if there's a best solution for this. Your answer certainly makes sense, I thought about that too, I'll do some experiments to see how viable it is, thanks very much for the suggestions.

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