ADSP-21371 program memory corruption
Hi, my name is Alessandro and I'm new in this community. I have a very strange issue in the development of a 21371 firmware for a CNC machine. Recently I made an apparently innocuous change in a C source file by adding a new "case" in a switch statement. The debug through ICE-1000 went good both in debug and release configurations so I moved to the LDR generation and the final programming of the firmware in flash memory (SPI flash). After the chip reset, the firmware loads correctly but the program image in memory is corrupted from a certain address. In particular the "main" function is corrupted as well so the machine do not starts.
I did a lot of tests to find the cause of the issue:
- The DXE file seems good as the program runs ok if loaded by the emulator
- I checked the content of the flash memory: it is correct and corresponds with the loaded LDR
- I found the address in program memory where the corruption starts and the corresponding position in the LDR file and in DXE.
Memory dump of working program
(DXE loaded from emulator)
Memory dump of corrupt program
(booted from flash)
...
[0020AAA0] 0x5FFEB1800000
[0020AAA1] 0x1002002A0C1B
[0020AAA2] 0x0F0100000043
[0020AAA3] 0x013E0000A021
[0020AAA4] 0x072000000004
[0020AAA5] 0x0F1400000005
---------------------------------------
[0020AAA6] 0x1114002AB8AD
[0020AAA7] 0x073E00000001
[0020AAA8] 0x073E00000001
[0020AAA9] 0x073E0000070F
[0020AAAA] 0x1000000E0BDE
[0020AAAB] 0x013E000CA000
[0020AAAC] 0x1004000E0BBD
[0020AAAD] 0x013E00130804
[0020AAAE] 0xAD08FFFFFFBC
...
...
[0020AAA0] 0x5FFEB180000
[0020AAA1] 0x1002002A0C1
[0020AAA2] 0x0F0100000043
[0020AAA3] 0x013E0000A02
[0020AAA4] 0x072000000004
[0020AAA5] 0x0F1400000005
<<< diffences start here and propagate to the rest of memory
[0020AAA6] 0x0001002AB8AD
[0020AAA7] 0x0001073E0000
[0020AAA8] 0x070F073E0000
[0020AAA9] 0x0BDE073E0000
[0020AAAA] 0xA0001000000E
[0020AAAB] 0x0BBD013E000C
[0020AAAC] 0x08041004000E
[0020AAAD] 0xFFBC013E0013
[0020AAAE] 0x0080AD08FFFF
...
It seems to me some sort of misalingment of the instruction codes as highlighted with colors.
Last but not the least, I found that the address where this starts is part of the "switch-case" statement code
I dont't know where to start to look for the issue. If I change the "case" value (for example from "case 215:" to "case 216:") the DXE content changes significantly (and also the position of routines in memory) and the problem disappears.
Any idea?
Audio Signal Processors
adsp-21371
ldr
SHARC Audio Processors/SoCs
in visual dsp ++
dxe
Show More
Further investigations. I started from begin by debugging the SPI kernel while it is fetching the LDR from flash. By adding some check on section headers I found where the issue begin. The address 0x0020AAA6 (48bit address space) is the second-last of its section which header is (TAG=0x00000004 - COUNT=0x0000FFFC - ADDRESS=0x00300000 (32bit address space)): the first address of next section should be: 0x00300000 + 0x0000FFFC = 30FFFC (32bit) = 20AAA8 (48bit).
But when the kernel loads the header of the following section this is what it founds (TAG=0x00000004 - COUNT=0x0000FFFC - ADDRESS=0x0030FFFA) which overlaps with the previus section, and is also not 48bit aligned because not multiple of 3! And this corresponds exactly with the content of the LDF file generated by visual dsp.
The problem is inside the LDR file!
Now it could be an issue of my custom LDF which is quite simple and worked ok for the last 6 years. Also I do not understand how this is related with the added "CASE 215:" in the switch statement...
Has anyone ever had this kind of problem?
Hello,
Can you please share your code to assist you better on this?
Best Regards,
Jithul
Hello!
As I said slight changes of any part of the source code would make the issue to disappear. I cannot give the entire project as it is property of my company and for me is impossible to create a test project to share, because as I delete part of the source codes the problem vanishes. I can share the DXE and LDR if you need, just to show the issue in the generation of the LDR section header.
Link to DXE
Link to LDR
Link to SPI Kernel
Visual DSP generates the LDR with this options:
elfloader.exe -proc ADSP-21371 -bSPI -fHEX -HostWidth 8 -NoBitReverse -l Kernel_21371_spi.dxe -t65530 -o .\Release\F16.ldr -NoInitialWord -v .\Release\F16.dxe -MM
The first section affected starts at line # 13723 of the LDR file:
:20A9EC0004000000FCFF0000FAFF3000010000003E07010000003E07120700003E07DE0B50
from where I extracted the header TAG=0x00000004 - COUNT=0x0000FFFC - ADDRESS=0x0030FFFA which starts a program memory sdram section which results to be not 48bit-aligned
Hello,
Sorry for the delayed response. From the information given above, I do not see anything obvious that has gone wrong.
I have couple of suggestion to debug the issue further.
1) Did you enable compiler optimization? If yes, can you please refer to below FAQ?
FAQ: Why does my code stop working when I enable optimization?
2) Do you have any of your code or data resides in SDRAM, in that case can you please confirm that the SDRAM configuration is done properly in the kernel file?
3) One way to debug your application which is not booting properly is to edit your boot-kernel.asm such that the first executed instruction is JUMP(PC,0);. This way, the part will load the boot-kernel and then just sit there executing the same instruction over and over again. After you reset the board and it starts booting, you connect the DSP with the emulator (be sure the session is configured to NOT reset upon connection), change that instruction to a NOP; in the disassembly window, and then step/run through the rest of the boot sequence. By this way you can exactly find the flow of your code.
Best Regards,
Jithul
Hello, to answer your questions:
1) No, the compiler optimizationa are not enabled
2) The firmware resides mostly on SDRAM but I'm sure the configuration is correct because the same code is shared by the kernel, the firmware and also the same values used to initialize the registers are also used in the XML customization file for the Visual DSP session. I remark that the program works ok if loaded by emulator, both in debug and release configuration.
3) That it exactly what I did to find out that the problem resides in the LDR file. By breaking the flash loading process in the kernel execution I found that from a certain address the LDR instructs the kernel to load a program memory section to a misaligned address and that breaks everything as the C main function is part of that section.
In the following image you can see how the program memory content (and the corresponding assembly) changes from the 20AAA8 address. On the left the correct values loaded from emulator, on the right the content loaded by the kernel from the LDR. It is not immediate but the corrupted memory is equal to the correct one, but misaligned of 2x32bit word (4/3 of a 48bit word) and a little scrambled by the endianness correction.
At the moment I solved by making some changes on the source code, for example by changing the case number in the switch case statement. But I'm really struggling to discover the cause of this issue!
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