Memory restriction in Core0(ARM) ADSPSC58x

Hello,

We would suggest you to refer the "ADSP-SC58x/ADSP-2158x Memory Map" Figure 5 of the adsp-sc58x datasheet and find the datasheet link below.
http://www.analog.com/media/en/technical-documentation/data-sheets/ADSP-SC582_583_584_587_589_ADSP-21583_584_587.pdf

Also we recommend you to refer the "SYSTEM INFRASTRUCTURE" section in datasheet which describes the system memory infrastructure of the ADSP-SC58x/ADSP-2158x processors.

Best Regards,

Jithul

Hi Jithul,
Thanks for your continues support.

In Core_0 adsp-sc58x-common.ld file L1 memory not present.L2 and L3 memory only available on Core0 .ld file.
In reference manual Figure-1 L1-Cache (32KB-Instruction cache,32KB-Data Cache) available.
where we need to check this L1 cache memory on Core0 and L2 Cache memory in document wise 256KB given at Figure_1.

Please provide where this cache memories available.

Please provide the feedback.

HI Jithul,

Thanks for your continues support.

Please clarify these below quires.

1. Figure_5 they given ARM address space range 0x00000000 to 0x20000000.But in .map file starting address 0x00000000,0x20008000 and 0x89000000 range available.

2. Figure_1:32KB Instruction cache and 32KB Data cache. Where we need to check these memory range.

3. Please provide Core0 L2 memory address ranges start and end address.

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Thank you,
EZ Admin

Are you looking at the .ld file in the below path.

C:\Analog Devices\CrossCore Embedded Studio 2.8.1\ARM\arm-none-eabi\arm-none-eabi\lib\sc589_rev_any?

Please confirm

Hi Jithul,

kindly provide the feedback for above quires.