ADAU1701 TDM In - I2S out
Hello,
in my current project I'm using an ADAU1701. On my system MCU I implemented an USB-to-TDM-Interface which delivers 8 channels with 24 bits at 48 kHz via TDM8.
The Masterclock is 24.576 MHz, the Bitclock is 8*32*48 kHz = 12.288 MHz.
At the output I have to use I2S, because my digitally sourced class-d amps don't support TDM. The clocks must be routed through the dsp (bclk_in to bclk_out, lrclk_in to lrclk_out).
The question is: Does the ADAU1701 reclock the clocks when using TDM at the input an I2S at the output?
On the input side I need a bitclock of 12.288 Mhz for TDM, at the output I need a 64 x fs = 3.072 MHz bitclock for I2S.
To test that config, I enabled the Master Mode at the output (which should word, because the whole system is running with the same MCLK, so all clocks are synchronized) and set the bclk to Internal/16 = 3.072 MHz. See my Hardware config below.
The basic question is, if the reclocking of the bclk is possible?
Kind regards,
Markus
Audio Signal Processors
i2s
master
reclocking
routing
SigmaDSP Audio Processors
tdm
slave
adau1701
Show More
Hello Markus,
The BCLK input on the serial input port are always a slave on this device. All it is used for is to clock in the data into a shift register.
The serial output port can be configured as a master or slave. As a master it divides down the master clock that is coming into the part so it is not related to the serial input port bit clock at all. They must all be ultimately derived from the same master clock to ensure that there are always the correct number of transitions in a frame but, we do not take the BCLK inputs and use that for anything more than the shift in data.
I hope that helps.
I think you will be fine setting the output port to be a master and sending out I2S signals.
Dave T
Please log in to reply.