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upgrading from a ADAU1761 on the ZEDBOARD

SigmaDSP & SigmaStudio DKF638 May 31, 2019 00:00 3 replies Original on forum ↗
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DKF638 Question
May 31, 2019 00:00

We are looking to upgrade from the ADAU1761 which came with our Digilent Zedboard. Everything about the 1761 is fine except for the sample rate - our application now requires the max sample rate of 192 kHz. We were looking at the ADAU1772 and the ADAU1701. I assumed there was a benefit to staying with the same ADAU 'family' ? I guess the first choice would be the ADAU1772 because it had better THD specs.

Configuration of the 1761 was dirt simple on the Zedboard so I'm hoping we can keep things simple going forward with the 1701 or 1772. We will be switching from the Zedboard to the Ultra96-V2 FPGA board and designing on our own custom codec board heavily based on codec schematics and layout which are provided as part of the 1701 or 1772 EVAL boards.

Can anyone at AD offer any advice here as we seek to upgrade ? Thanks.

Audio Signal Processors

adau1772

Integrated/Special Purpose A/D Converters

SigmaDSP Audio Processors

adau1761

Audio CODECs

adau1701

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DaveThib Reply
May 31, 2019 00:00

Hello DKF638,

The 1701 is a great little DSP. But it is an older version of the SigmaDSP core from the 1761. They are pretty close and one great advantage is that it does have selfboot capability that the 1761 does not have. They both will do close to 1024 instructions per sample period but the 1761 is a little more efficient.

A lot of the choice of which part will depend on your application. How many channels? What kind of processing do you need and how much of it? There are many more questions that can be asked.

The ADAU1772 does not have a full-function DSP core in it. It has what we call a fast core. It is designed to process a number of Bi-Quad filters VERY fast. I am guessing this is not the application you need.

There is a new part with better specs that has a fast core and a DSP core just like the 1761. It is the ADAU1787 but there are a few details that might make using it difficult. First, it is available only in a wafer level part so the PCB design is more difficult. Then it only runs on a max of 1.8V for AVDD power.

Our best DSPs are the ADAU1452 and ADAU1467 families of parts. These are very powerful parts but lack built in ADCs and DACs. So it makes the system design a little more complicated.

By the way, by going up to 192kHz fs you will only have 256 instructions per sample period. So this may be a limitation. In contrast the ADAU1452 will have 1,536 instructions per sample period at 192kHz fs and it is much more efficient with each instruction period.

Dave T

DKF638 Reply
Jun 5, 2019 00:00

Dave:

Attached below is our configuration code for the ADAU1761. I am only including it because, being very much a novice here, I am not sure how many 'instructions per sample' we might require. We do not have code for the ADAU1761 (besides reading from it and writing to it) other than what is attached below. Our signal processing is somewhat unique and is handled in our FPGA. So, I guess my question is: if we were to replace the ADAU1761 with the ADAU1701 and configure it similarly as shown below with the exception that we would be increasing our sample rate to ~130 kHz, would we be okay ? I’m looking for the easiest migration from the 1761 to a codec capable of operation at our new sample rate. I would prefer to use a codec with integral ADC/DAC just to simplify our custom hardware development. I’m guessing the 1701 will most easily meet our needs. We will need 4 RF input channels and 4 RF output channels so we will need 2 codecs (just like we do now with a pair of 1761’s).

Just out of curiosity, will the configuration script for the 1701 be similar to what is attached below for the 1761 ?

Thanks very much for your assistance.

Regards,

DKF638

--------------------------

#!/usr/bin/env python

from zed_adau1761_i2c import zed_adau1761_i2c_write_block

# Clock Control Register; core clock enabled

zed_adau1761_i2c_write_block(0x4000, [0x1])

# Clock Enable0; enable all digital clock engines

zed_adau1761_i2c_write_block(0x40f9, [0x7f])

# Clock Enable1; enable Digital Clock Generators 0 & 1

zed_adau1761_i2c_write_block(0x40fa, [0x3])

# Record Mixer Left (Mixer1, M1) Control0; M1 enabled, Record Mixer Left (Mixer1, M1)

zed_adau1761_i2c_write_block(0x400a, [0x01, 0x05])

# Record Mixer Right (Mixer2, M2) Control0; M2 enabled, Record Mixer Right (Mixer2, M2) Control1; 0 dB gain for Aux input

zed_adau1761_i2c_write_block(0x400c, [0x01, 0x05])

# ADC Control; left/right ADCs ON

zed_adau1761_i2c_write_block(0x4019, [0x33])

# Serial Input Route Control; setting lsb high configures serial output to ADCs

zed_adau1761_i2c_write_block(0x40f3, [0x01])

# Playback Mixer Left (Mixer3, M3) Control0; M3 enabled, left DAC unmuted to M3

zed_adau1761_i2c_write_block(0x401c, [0x21])

# Playback Mixer Right (Mixer4, M4) Control0; M3 enabled, right DAC unmuted to M4

zed_adau1761_i2c_write_block(0x401e, [0x41])

# Playback L/R Mixer Left (Mixer5, M5) LineOutputControl; M4 output muted, M3 output unmuted with 0dB gain, M5 enabled

zed_adau1761_i2c_write_block(0x4020, [0x05])

# Playback L/R Mixer Right (Mixer6, M6) LineOutputControl; M3 output muted, M4 output unmuted with 0dB gain, M6 enabled

zed_adau1761_i2c_write_block(0x4021, [0x11])

# Playback Line Output Left Volume Control; 0 dB gain, line output unmuted for left channel, Playback Line Output Right Volume Control; 6 dB gain, line output unmuted for right channel

zed_adau1761_i2c_write_block(0x4025, [0xe6, 0xe6])

# Playback Power Management; left/right channels enabled

zed_adau1761_i2c_write_block(0x4029, [0x03])

# DAC Control0; left/right DACs ON

zed_adau1761_i2c_write_block(0x402a, [0x03])

# 96 kHz

zed_adau1761_i2c_write_block(0x4017, [0x6])

# Serial Input Route Control; setting lsb high configures serial input to DACs

zed_adau1761_i2c_write_block(0x40f2, [0x01])

# Serial Port Control1; # bit clock cycles per LRCLK frame = 64 (default), left data first, bit clock cycle delay = 1

zed_adau1761_i2c_write_block(0x4016, [0x0])

DaveThib Reply
Jun 6, 2019 00:00

Hello DKF638,

OK, so you are not using the DSP core at all. You are simply using this as a codec. In that case you could use the ADAU1361 which is the same codec minus the DSP. But you would only be able to go up to 96kHz fs.

I would take a look at the ADAU1372 a little more closely. You will still need two of them but there are some advantages. The big one is that clocking is really easy. It can operate using its own master clock, or some other one from your system and it can be at almost any frequency within reason. It has a fractional PLL. Then the serial ports all go through sample rate converters on the way out and in. So if they are configured as slaves, then all you need to feed it is bit clock and frame clock, and data, and it will follow it. It does not have to be correlated with the master clock at all. So for an RF application where the sampling rate may be drifting and there is no master clock it is perfect. It will simply follow the sampling rate. No intervention required. They can be daisy chained if you are low on serial ports. They can do TDM 8 but no more than that. So they will run up to 192kHz and a non-standard rate of 130kHz is no problem at all.

The 1701 can be used as just a codec as well but if I am remembering right, you would have to run through the DSP core and so you would have to load in a program. Yes, I just checked, you would have to use the core for routing the audio so it would be more complicated and the master clock and PLL will all have to be setup properly for it to work.

I say you look into the ADAU1372.

Dave T