External SPI Delay on ADAU1466
I am working on a project that requires a significant amount of delay. Altough all of the examples I've found concerning external SPI delay refer to the ADAU1452, I find that SigmaStudio shows the option for the ADAU1466. My first question is, has anybody successfully implemented a larger (4 to 8mb) SPI RAM with the 1466?
I understand that the External SPI Delay will address up to 32MB. The largest production memory I can find from sources like DigiKey are FRAM devices like CY15B108QI. Has anybody used this family of parts with SigmaDSP devices successfully? If I can find / configure something larger, can it be used?
Audio Signal Processors
adau1452
external delay
sigmastudio
SigmaDSP Audio Processors
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Hi Laserguru,
Thank you for your question.
The external SPI delay will work identically on the ADAU1466 and ADAU1452. In fact, any project written for the ADAU1452 will work perfectly on the ADAU1466! On the ADAU146x parts, additional features and memory were added, but no logic was removed.
I am working on an answer regarding large memory sizes and will make another post about that.
Please note that as of SigmaStudio 4.5, we are aware of some issues with the SPI Delay block and are working to fix them. In the meantime, you may wish to know these details:
Currently only one channel of delay is possible per physical RAM chip.
There is an offset in the delay you enter. The actual delay you will get is one higher than what you enter.
Because of this, you may enter values from 1 (which will give you 2 samples delay) up to Max-1 (which will give you Max samples).
If you would like to use 0 and 1 sample delays, the schematic below may help. For delays of 0 or 1, you can use internal DSP memory, and for delays greater than 1 you can use the SPI memory.
Joshua
Hi Laserguru,
Based on a quick glance at the datasheet for the FRAM you found, I would expect that device to work with the ADAU1466 since its SPI implementation is nearly identical to SRAMs we have used in the past.
Regarding the maximum capacity you can use, the External SPI Delay block uses 24-bit addresses. Since each address corresponds to 8 bits of data, the theoretical maximum delay memory is 128MBits or 16 MBytes.
Below is a brief list of requirements for potential higher-capacity RAMs.
The device must operate at the SigmaDSP's IOVDD voltage
The device must support SPI Mode 3
Sequential read and write should be supported
The SRAM chips we have tested have one command byte and three address bytes (24 bits).
Does that answer your question?
Joshua
Thank you for the responses. This is very helpful.
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