ADAU1787 BCLK when external 24.576MHz MCLK provided, PLL bypassed

I do not see anything in the data indicating how the ADAU1787 BCLK is generated when an external 24.576MHz MCLK provided and the PLL bypassed.

Is there a more detailed clock routing diagram (including FS) or can I be affirmed BCLK = MCLK in this case if I set the BCLK to 24.576MHz?

Thanks,

Dan

bclk

ADAU1787

mclk

Integrated/Special Purpose A/D Converters

Audio CODECs