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Q&A from Analog Devices EngineerZone: SigmaDSP/SigmaStudio and DSP discussions (9 topics).
9 topics · 44 messages
Filtered by: #bclk ✕
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ADAU1701 IIS input 192Khz signal to enable filter, DAC playback has noise
Specific operation description: As shown in the schematic diagram above, currently only one General 2nd filter is added, set to hpf and 60Hz corner frequency. Set the sample rate to 192K and the DSP c
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BCLK Settings, Sampling Point or Format Selection
Hello together, we have a question regarding the selection of the BCLK settings in SigmaDSPs. The best would be to share an example. SigmaDSP Serial In Settings: When we assume that we configured the
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ADAU1401 with PCM5102 DAC, BCLK missing
UPDATE: My scope was not good, later I managed to measure properly. DATA, LRCK, BCLK frequencies+voltages from the ADAU ok. But maybe i found what cause the issue: PCM5102 voltage pins: - pin 1 CPVDD:
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I2S signal frequency relation between ADAU1450 & AK4621, please verify
Hello I am running ADAU1450 in FS 96khz mode along with Codec AK4621 configured for the same sampling frequency mode. I am getting below readings MCLK 12.288 MHZ LRCLK 96 KHZ BCLK 6.14 MHZ SDATA_IN3 7
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Interfacing ADAU1452/50 DSP with CS4272 CODEC
Can someone please tell me how to configure LRCLK IN / OUT and BCLK IN / OUT of ADAU1452 when interfacing with codecs like CS4272 which only have single BCLK and LRCLK pins?? I am confused on this iss
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MCLKIN & BCLK synchrony in ADAU1701
Hi, I'm try to design an I2S communication system with a uC and ADAU1701. uC has to be master in I2S and obtain the digital audio from ADAU1701. ADAU1701 has an crystal of 12.288MHz as source clock, b
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How to route TDM audio through multiple ADAU1701s?
Hello all, We're developing an audio mixer around a ring of ADAU1701s where each receives a TDM steam from its neighbor, adds in two analog inputs and sends the mix through to the next -1701. The bloc
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ADAU1701 - Problem occurs when using S-DATA INPUT
hello. I have problem of when using ADAU1701 I2S. And i2s of ADAU1701 is slave mode. Master is MCU. however, this MCU is not bring to i2s function. So. I made self to LRCLK-OUT and BCLK-OUT, and S_DAT
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AD1937 - Can I set ABCLK per frame to over 64cycles in I2S stereo mode?
Hello, AD engineers. I am using AD1937 for recording and I am just checking ad1937 for what kind of BCLK and LRCLK I can use when I record. I have several questions about BCLK frequency for ADC operat