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ADAU1787 i2s input to DAC Output with filters

SigmaDSP & SigmaStudio fmvoxa Feb 28, 2022 00:00 2 replies Original on forum ↗
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fmvoxa Question
Feb 28, 2022 00:00

Hello,

I want to pass the incoming i2s signal (from a bluetooth to i2s device) to EQ Filter and then as output to the DAC. I used this as an example, but removed the FDEC: ADAU1787 two-way bluetooth streaming over I2S

But I want in the schematic an EQ Filter so change the parameter of the audio signal before passing it to the DAC Output. I can't connect the ASRC output to any function block.

I think I didn't set the register correctly.

And the schematic:

In the example, was the FDEC used. Is this necessary? In my example, it is working to without it.

My example is without FDEC and working too.

Test_Adau1787_i2s_dac.dspproj

Thanks and greetings!

fmvoxa

ADAU1787

i2s input

dac output

i2s

schematic

Integrated/Special Purpose A/D Converters

Audio CODECs

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SPT_CTRL.png
SPT_CTRL.png
ASRC_CTRL.png
ASRC_CTRL.png
DAC_CTRL_2.png
DAC_CTRL_2.png
6170.schematic.png
6170.schematic.png
fmvoxa Reply
Feb 28, 2022 00:00

Ok. I think I need the FDEC. The filter must bei set in the SigmaDSP. So I need the FDEC from SDSP to FDSP. But I don't know how to route from Seriel In to the SDSP and then to the DAC.

galvinpjg Reply
May 5, 2022 00:00

fmvoxa,

What is the desired sampling rate for the FDSP, SDSP, DAC and Serial Port? Based on the schematic you sent, it is currently set up so that the ASRCI outputs at 192kHz. The ADCs are enabled and set to 192kHz, and are also used for FDSP_RATE_SOURCE (ADC0/1) and SDSP_RATE_SOURCE (ADC2/3), so that the FDSP/SDSP sampling rate is 192kHz. The DAC_FS is also set to 192kHz. In this scenario, the FDEC is not needed since all the rates are already equal. Is this intended?

The schematic currently does not show any SDSP processing, so I am also unsure where the SDSP outputs are intended to go. I have made an example project for now that only uses ASRCI --> FDSP---> DACOUT with one EQ in the FDSP path. I hope this helps but please let me know if more is needed in the schematic window, or if there is more information on the desired signal paths and sample rates.

Thanks,

galvinpjg

Updated_Test_Adau1787_i2s_dac(fdsp).dspproj