ADAU1452 predesign stage: second spdif dir, Auto EQ , 8 band parametric eq hardware related too
Hello,
i have some questions about the Automatic EQ feature:
Once i build the complete sigma studio project for the ADAU1452 can i later update all MLSSA values with an
microcontroller using I2C ? I read that in some cases the ADAU offeres fixed memory adresses for the coefficients.
I need the same manipulation feature for the parametric eq too because i want to use my own microcontroller gui
for EQing and headroom adjustments.
My system uses two stereo dacs and 45 and 49Mhz clocks as mclk to support samplerates >=356khz.
The ADAU doesn't support an mclk that high. I assume i need an extra clock for the ADAU ?
Maincontroller is the xmos usb bridge or the two independant running spdif inputs eg TV and PS5.
Setup:
I have to use an extra second spdif receiver for two independant stereo spdif inputs -> ASRC, on input 4
ADC : 32 bit 2 channel pcm on dsp input 3. eq' ing and routed to output 1 or 2.
2 x 32 bit stereo pcm from XMOS USB -> L1 &R1 and L2&R2 on DSP Input 0 and Input 1 + B_clk and Frame_clock.
DSP will be hold in reset for DoP, DSD mode and samplerates >=352kHz
Is the ADAU1452 capable of : 8 band eq independant on each stereo channel + Automatic EQ + ASRC for the extra spdif at max 192kHz?
Big thanks
Best regards
Andreas
Hello Andreas,
I will clarify some of your questions.
Biquads said:
I read that in some cases the ADAU offeres fixed memory adresses for the coefficients.
There is feature called IPAT that will hold a fixed memory for a parameter for the uC to access. Please refer to IPAT here.
Biquads said:
The ADAU doesn't support an mclk that high. I assume i need an extra clock for the ADAU ?
The is indeed high. The datasheet says it should be between 2.375MHz and 36MHz. However, usually MCLK into the DSP will be 12.288MHz or you can also use 24.576MHz and adjust it accordingly in the pre divider to derive the usual system clock of 294.912MHz.
Biquads said:
I have to use an extra second spdif receiver for two independant stereo spdif inputs
There is only one stereo SPDIF Tx and Rx is available in this processor. Acc to the datasheet, the SPDIF Rx sample rate must be within 18KHz to 96KHz.
Biquads said:
DSD mode and samplerates >=352kHz
Is your core rate 352KHz or above? I don't think you can go over 192KHz.
Biquads said:
can i later update all MLSSA values with an
microcontroller using I2C ?
I will answer this in a little while.
Regards,
Harish
Thank you Harish,
that clears also of questions. I will follow your suggestions and use an extra multiplexer to "bridge or disable" the DSP at samplerates higher than
192kHz.
I will use an extra 24.576MHz dsp clock. Thanks.
Important for me is the MLSSA value question. I need to update this values locally too.
Regards,
Andreas
HI Harish,
any news about MLSSA Auto EG I2C microcontroller updates ?
Hello Biquads,
I don't really think you can update the values from uC, since it is not stored in any memory of the DSP. SigmaStudio only uses the MLSSA file to display the speaker response; it does not generate filters to adjust the response to a target.
You can see in the capture window that only filter coefficients of this blocks have been sent to the DSP. So, by using uC, you can only access the parameters that is stored in the RAM like the coeffs.
Regards,
Harish
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