ADAU1761 starts outputting noise at maximum gain
Hi!
We have an issue with the ADAU1761 running FW created in SigmaStudio. The chip starts to output rather random signals at times until it has been reset, such as a sine tone around 1 kHz, but also a pulse-like noise signal, both at maximum gain. We've been using the ADAU1761 for a couple of years without seeing this problem until recently, where it appears in ~0.2% of the instances we run. But since the speaker driver that is connected to the codec is capable of a high SPL output, this becomes a serious issue, since it also blocks whatever signal the speaker is supposed to output.
I've been trying to dig around a bit in the EngineeringZone and found a couple of related problems, most notably https://ez.analog.com/dsp/sigmadsp/f/q-a/64225/adau1701-dsp-setup-error. We're running ADAU1761 in 48 kHz and thus have a limit of 1024 instructions where 1013 instructions are being used. Could this be problematic or is it related to something else?
I've also tried setting up the watchdog with a polling function to see if the register value changes, but it's a bit unclear how exactly the watchdog should be configured in terms of register settings (can't get it to trigger regardless of instruction limit).
Best regards,
Niklas
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ADAU1761BCPZ
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Hello Niklas,
I do not have an answer about the watchdog feature. I have never seen anyone use it and so there may be an issue there.
You are correct to think about the instruction limit. You might be hitting it. With this core the symptom you will see if the frame was overrun is that a sample will be missed. In other cores there will be code that is not reached when the end of frame interrupt comes it will start the program back at the beginning. In this core the interrupt is masked until the program finishes. So it will ignore the end of frame and finish the program, then it enables the interrupt and waits for the new frame start pulse and in this case it is the end of the next frame. The result is that you are running at half the sample rate if this happens most of the time. So then you can get aliasing and that is what you may be hearing with the 1kHz tone.
What is your master clock frequency coming into the MCLKI pin?
What do you have for the core start pulse setting? This is the DSP Sampling Rate Register, R57. What is it set to?
If you have it set to one of the external sources, the serial port in or out. Then the number of instructions depends on the incoming sample rate and the exact frequency of the master clock coming into the part and that drives the frequency of the PLL output. So obviously the PLL settings will determine the internal system core clock frequency and divide that by the sample rate and you have the number of instructions available. So if you are using an asynchronous source, then the number of instructions will change as oscillators drift.
I am heading out on vacation so my response might be a little delayed. I will try to check the forum while I am gone. this is why this answer is a little longer...
If you want to share your program I might be able to find some places where a few instructions could be saved. You can send it to me via PM if you need to keep confidentiality.
Dave T
Hi Dave!
The reason we wanted to setup the watchdog was the possibility of being able to monitor this behavior and taking action if we detect that the device ends up in this state, but I guess that's irrelevant if we find the root cause instead.
Interesting, is there any official recommendation on how many instructions are needed as overhead? Currently we have reduced the number of instructions to 973, do you think that would be sufficient?
As for your questions, the MCLK frequency is 12.288 MHz and we're using the internal PLL. R57 is set to 0001 (48 kHz).
I would like to share the program but I'll have to sync with our team first, I'll get back to you on that.
Thank you for the quick response though. Have a nice vacation!
BR,
Niklas
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